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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1998-10-19 18:25:16 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1998-10-19 18:25:16 +0000 |
| commit | 8eba4708f068826fd826db22f6bcdff69aae908a (patch) | |
| tree | 0f8036edcefd19bc582f28e3028b685d0572090c /doc/supplements/i386/timeFORCE386.t | |
| parent | All files as automatically generated as possible. (diff) | |
| download | rtems-8eba4708f068826fd826db22f6bcdff69aae908a.tar.bz2 | |
Nearly everything that can be is now automatically generated.
Diffstat (limited to 'doc/supplements/i386/timeFORCE386.t')
| -rw-r--r-- | doc/supplements/i386/timeFORCE386.t | 42 |
1 files changed, 0 insertions, 42 deletions
diff --git a/doc/supplements/i386/timeFORCE386.t b/doc/supplements/i386/timeFORCE386.t index 0049c1fdcd..88d8ea09cf 100644 --- a/doc/supplements/i386/timeFORCE386.t +++ b/doc/supplements/i386/timeFORCE386.t @@ -11,36 +11,8 @@ \global\advance \smallskipamount by -4pt @end tex -@ifinfo -@node CPU386 Timing Data, CPU386 Timing Data Introduction, Timing Specification Terminology, Top -@end ifinfo @chapter CPU386 Timing Data -@ifinfo -@menu -* CPU386 Timing Data Introduction:: -* CPU386 Timing Data Hardware Platform:: -* CPU386 Timing Data Interrupt Latency:: -* CPU386 Timing Data Context Switch:: -* CPU386 Timing Data Directive Times:: -* CPU386 Timing Data Task Manager:: -* CPU386 Timing Data Interrupt Manager:: -* CPU386 Timing Data Clock Manager:: -* CPU386 Timing Data Timer Manager:: -* CPU386 Timing Data Semaphore Manager:: -* CPU386 Timing Data Message Manager:: -* CPU386 Timing Data Event Manager:: -* CPU386 Timing Data Signal Manager:: -* CPU386 Timing Data Partition Manager:: -* CPU386 Timing Data Region Manager:: -* CPU386 Timing Data Dual-Ported Memory Manager:: -* CPU386 Timing Data I/O Manager:: -* CPU386 Timing Data Rate Monotonic Manager:: -@end menu -@end ifinfo -@ifinfo -@node CPU386 Timing Data Introduction, CPU386 Timing Data Hardware Platform, CPU386 Timing Data, CPU386 Timing Data -@end ifinfo @section Introduction The timing data for the i386 version of RTEMS is @@ -51,9 +23,6 @@ understanding of each directive time provided. Also, provided is a description of the interrupt latency and the context switch times as they pertain to the i386 version of RTEMS. -@ifinfo -@node CPU386 Timing Data Hardware Platform, CPU386 Timing Data Interrupt Latency, CPU386 Timing Data Introduction, CPU386 Timing Data -@end ifinfo @section Hardware Platform All times reported except for the maximum period @@ -73,9 +42,6 @@ cycles executed with interrupts disabled, including the instructions to disable and enable interrupts, was divided by 16 to simulate a i386 executing at 16 Mhz. -@ifinfo -@node CPU386 Timing Data Interrupt Latency, CPU386 Timing Data Context Switch, CPU386 Timing Data Hardware Platform, CPU386 Timing Data -@end ifinfo @section Interrupt Latency The maximum period with interrupts disabled within @@ -98,9 +64,6 @@ vector and entry overhead time was generated on the Force Computers CPU386 benchmark platform using the int instruction as the interrupt source. -@ifinfo -@node CPU386 Timing Data Context Switch, CPU386 Timing Data Directive Times, CPU386 Timing Data Interrupt Latency, CPU386 Timing Data -@end ifinfo @section Context Switch The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS @@ -136,8 +99,3 @@ coprocessor is task specific. The following table summarizes the context switch times for the Force Computers CPU386 benchmark platform: -@include timetbl.texi - -@tex -\global\advance \smallskipamount by 4pt -@end tex |