path: root/doc/supplements/i386/timeFORCE386.t
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authorJoel Sherrill <>2006-08-23 19:11:14 +0000
committerJoel Sherrill <>2006-08-23 19:11:14 +0000
commit83fb86f32b73942be758c22423c0bfe506fd4ff6 (patch)
treed51a136781eaccf67bfb2addfbe5330d9aed4791 /doc/supplements/i386/timeFORCE386.t
parente8beb87007f4036b2900650f0576e4b3097636b8 (diff)
2006-08-23 Joel Sherrill <>
*,, FAQ/stamp-vti, FAQ/version.texi, common/cpright.texi: Merging CPU Supplements into a single document. As part of this removed the obsolete and impossible to maintain size and timing information. * cpu_supplement/.cvsignore, cpu_supplement/, cpu_supplement/arm.t, cpu_supplement/i386.t, cpu_supplement/m68k.t, cpu_supplement/mips.t, cpu_supplement/powerpc.t, cpu_supplement/preface.texi, cpu_supplement/sh.t, cpu_supplement/sparc.t, cpu_supplement/tic4x.t: New files. * supplements/.cvsignore, supplements/, supplements/, supplements/arm/.cvsignore, supplements/arm/BSP_TIMES, supplements/arm/ChangeLog, supplements/arm/, supplements/arm/arm.texi, supplements/arm/bsp.t, supplements/arm/callconv.t, supplements/arm/cpumodel.t, supplements/arm/cputable.t, supplements/arm/fatalerr.t, supplements/arm/intr_NOTIMES.t, supplements/arm/memmodel.t, supplements/arm/preface.texi, supplements/arm/timeBSP.t, supplements/c4x/.cvsignore, supplements/c4x/BSP_TIMES, supplements/c4x/ChangeLog, supplements/c4x/, supplements/c4x/bsp.t, supplements/c4x/c4x.texi, supplements/c4x/callconv.t, supplements/c4x/cpumodel.t, supplements/c4x/cputable.t, supplements/c4x/fatalerr.t, supplements/c4x/intr_NOTIMES.t, supplements/c4x/memmodel.t, supplements/c4x/preface.texi, supplements/c4x/timeBSP.t, supplements/i386/.cvsignore, supplements/i386/ChangeLog, supplements/i386/FORCE386_TIMES, supplements/i386/, supplements/i386/bsp.t, supplements/i386/callconv.t, supplements/i386/cpumodel.t, supplements/i386/cputable.t, supplements/i386/fatalerr.t, supplements/i386/i386.texi, supplements/i386/intr_NOTIMES.t, supplements/i386/memmodel.t, supplements/i386/preface.texi, supplements/i386/timeFORCE386.t, supplements/m68k/.cvsignore, supplements/m68k/ChangeLog, supplements/m68k/MVME136_TIMES, supplements/m68k/, supplements/m68k/bsp.t, supplements/m68k/callconv.t, supplements/m68k/cpumodel.t, supplements/m68k/cputable.t, supplements/m68k/fatalerr.t, supplements/m68k/intr_NOTIMES.t, supplements/m68k/m68k.texi, supplements/m68k/memmodel.t, supplements/m68k/preface.texi, supplements/m68k/timeMVME136.t, supplements/m68k/timedata.t, supplements/mips/.cvsignore, supplements/mips/BSP_TIMES, supplements/mips/ChangeLog, supplements/mips/, supplements/mips/bsp.t, supplements/mips/callconv.t, supplements/mips/cpumodel.t, supplements/mips/cputable.t, supplements/mips/fatalerr.t, supplements/mips/intr_NOTIMES.t, supplements/mips/memmodel.t, supplements/mips/mips.texi, supplements/mips/preface.texi, supplements/mips/timeBSP.t, supplements/powerpc/.cvsignore, supplements/powerpc/ChangeLog, supplements/powerpc/DMV177_TIMES, supplements/powerpc/, supplements/powerpc/PSIM_TIMES, supplements/powerpc/bsp.t, supplements/powerpc/callconv.t, supplements/powerpc/cpumodel.t, supplements/powerpc/cputable.t, supplements/powerpc/fatalerr.t, supplements/powerpc/intr_NOTIMES.t, supplements/powerpc/memmodel.t, supplements/powerpc/powerpc.texi, supplements/powerpc/preface.texi, supplements/powerpc/timeDMV177.t, supplements/powerpc/timePSIM.t, supplements/sh/.cvsignore, supplements/sh/BSP_TIMES, supplements/sh/ChangeLog, supplements/sh/, supplements/sh/bsp.t, supplements/sh/callconv.t, supplements/sh/cpumodel.t, supplements/sh/cputable.t, supplements/sh/fatalerr.t, supplements/sh/intr_NOTIMES.t, supplements/sh/memmodel.t, supplements/sh/preface.texi, supplements/sh/sh.texi, supplements/sh/timeBSP.t, supplements/sparc/.cvsignore, supplements/sparc/ChangeLog, supplements/sparc/ERC32_TIMES, supplements/sparc/, supplements/sparc/bsp.t, supplements/sparc/callconv.t, supplements/sparc/cpumodel.t, supplements/sparc/cputable.t, supplements/sparc/fatalerr.t, supplements/sparc/intr_NOTIMES.t, supplements/sparc/memmodel.t, supplements/sparc/preface.texi, supplements/sparc/sparc.texi, supplements/sparc/timeERC32.t, supplements/template/.cvsignore, supplements/template/BSP_TIMES, supplements/template/ChangeLog, supplements/template/, supplements/template/bsp.t, supplements/template/callconv.t, supplements/template/cpumodel.t, supplements/template/cputable.t, supplements/template/fatalerr.t, supplements/template/intr_NOTIMES.t, supplements/template/memmodel.t, supplements/template/preface.texi, supplements/template/template.texi, supplements/template/timeBSP.t: Removed.
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-@c COPYRIGHT (c) 1988-2002.
-@c On-Line Applications Research Corporation (OAR).
-@c All rights reserved.
-@c $Id$
-@include common/timemac.texi
-\global\advance \smallskipamount by -4pt
-@end tex
-@chapter CPU386 Timing Data
-@section Introduction
-The timing data for the i386 version of RTEMS is
-provided along with the target dependent aspects concerning the
-gathering of the timing data. The hardware platform used to
-gather the times is described to give the reader a better
-understanding of each directive time provided. Also, provided
-is a description of the interrupt latency and the context
-switch times as they pertain to the i386 version of RTEMS.
-@section Hardware Platform
-All times reported except for the maximum period
-interrupts are disabled by RTEMS were measured using a Force
-Computers CPU386 board. The CPU386 is a 16 Mhz board with zero
-wait state dynamic memory and an i80387 numeric coprocessor.
-One of the count-down timers provided by a Motorola MC68901 was
-used to measure elapsed time with one microsecond resolution.
-All sources of hardware interrupts are disabled, although the
-interrupt level of the i386 allows all interrupts.
-The maximum period interrupts are disabled was
-measured by summing the number of CPU cycles required by each
-assembly language instruction executed while interrupts were
-disabled. Zero wait state memory was assumed. The total CPU
-cycles executed with interrupts disabled, including the
-instructions to disable and enable interrupts, was divided by 16
-to simulate a i386 executing at 16 Mhz.
-@section Interrupt Latency
-The maximum period with interrupts disabled within
-RTEMS is less than RTEMS_MAXIMUM_DISABLE_PERIOD microseconds
-including the instructions
-which disable and re-enable interrupts. The time required for
-the i386 to generate an interrupt using the int instruction,
-vectoring to an interrupt handler, and for the RTEMS entry
-overhead before invoking the user's interrupt handler are a
-total of 12 microseconds. These combine to yield a worst case
-interrupt latency of less
-microseconds. [NOTE: The
-maximum period with interrupts disabled within RTEMS was last
-It should be noted again that the maximum period with
-interrupts disabled within RTEMS is hand-timed. The interrupt
-vector and entry overhead time was generated on the Force
-Computers CPU386 benchmark platform using the int instruction as
-the interrupt source.
-@section Context Switch
-The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS
-microseconds on the Force Computers CPU386 benchmark platform.
-This time represents the raw context switch time with no user
-extensions configured. Additional execution time is required
-when a TASK_SWITCH user extension is configured. The use of the
-TASK_SWITCH extension is application dependent. Thus, its
-execution time is not considered part of the base context switch
-Since RTEMS was designed specifically for embedded
-missile applications which are floating point intensive, the
-executive is optimized to avoid unnecessarily saving and
-restoring the state of the numeric coprocessor. The state of
-the numeric coprocessor is only saved when a FLOATING_POINT task
-is dispatched and that task was not the last task to utilize the
-coprocessor. In a system with only one FLOATING_POINT task, the
-state of the numeric coprocessor will never be saved or
-restored. When the first FLOATING_POINT task is dispatched,
-RTEMS does not need to save the current state of the numeric
-The exact amount of time required to save and restore
-floating point context is dependent on the state of the numeric
-coprocessor. RTEMS places the coprocessor in the initialized
-state when a task is started or restarted. Once the task has
-utilized the coprocessor, it is in the idle state when floating
-point instructions are not executing and the busy state when
-floating point instructions are executing. The state of the
-coprocessor is task specific.
-The following table summarizes the context switch
-times for the Force Computers CPU386 benchmark platform: