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author | Hesham ALMatary <heshamelmatary@gmail.com> | 2014-08-16 11:30:19 -0500 |
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committer | Joel Sherrill <joel.sherrill@oarcorp.com> | 2014-08-20 15:46:15 -0500 |
commit | b08829228d2efc6c506fa3a05b0266baf70f8681 (patch) | |
tree | 96d57b6d431adc61c9e3c688a4a14004278e625f /doc/cpu_supplement/or1k.t | |
parent | libbsp/arm/acinclude.m4: Regenerate for tms570 (diff) | |
download | rtems-b08829228d2efc6c506fa3a05b0266baf70f8681.tar.bz2 |
Add new documentation section for OpenRISC CPU architecture.
Diffstat (limited to '')
-rw-r--r-- | doc/cpu_supplement/or1k.t | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/doc/cpu_supplement/or1k.t b/doc/cpu_supplement/or1k.t new file mode 100644 index 0000000000..4f1bf18c36 --- /dev/null +++ b/doc/cpu_supplement/or1k.t @@ -0,0 +1,76 @@ +@c +@c COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> +@c All rights reserved. + +@ifinfo +@end ifinfo +@chapter OpenRISC 1000 Specific Information + +This chapter discusses the +@uref{http://opencores.org/or1k/Main_Page, OpenRISC 1000 architecture} +dependencies in this port of RTEMS. There are many implementations +for OpenRISC like or1200 and mor1kx. Currently RTEMS supports basic +features that all implementations should have. + +@subheading Architecture Documents + +For information on the OpenRISC 1000 architecture refer to the +@uref{http://openrisc.github.io/or1k.html,OpenRISC 1000 architecture manual}. + +@section Calling Conventions + +Please refer to the +@uref{http://openrisc.github.io/or1k.html#__RefHeading__504887_595890882,Function Calling Sequence}. + +@subsection Floating Point Unit + +A floating point unit is currently not supported. + +@section Memory Model + +A flat 32-bit memory model is supported. + +@section Interrupt Processing + +OpenRISC 1000 architecture has 13 exception types: + +@itemize @bullet + +@item Reset +@item Bus Error +@item Data Page Fault +@item Instruction Page Fault +@item Tick Timer +@item Alignment +@item Illegal Instruction +@item External Interrupt +@item D-TLB Miss +@item I-TLB Miss +@item Range +@item System Call +@item Floating Point +@item Trap + +@end itemize + +@subsection Interrupt Levels + +There are only two levels: interrupts enabled and interrupts disabled. + +@subsection Interrupt Stack + +OpenRISC RTEMS port uses RTEMS SW interrupt stack. +The stack for interrupts is allocated during interrupt driver initilization. +When an interrup entered, the _ISR_Handler routine is resposible for +switching from the interrupted task stack to RTEMS SW interrupt stack. + +@section Default Fatal Error Processing + +The default fatal error handler for this architecture performs the +following actions: + +@itemize @bullet +@item disables operating system supported interrupts (IRQ), +@item places the error code in @code{r0}, and +@item executes an infinite loop to simulate a halt processor instruction. +@end itemize |