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| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-07-03 17:26:50 +0200 |
|---|---|---|
| committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-10-02 10:40:33 +0200 |
| commit | a114f99bd28cd534b1446d2d85ea681ef1832955 (patch) | |
| tree | 44b9310939d888604b61e59ab1191436ab8f4ffb /depcomp | |
| parent | bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310. (diff) | |
| download | rtems-a114f99bd28cd534b1446d2d85ea681ef1832955.tar.bz2 | |
bsps/arm: Change code to explicit selection of cache implementation for ARM BSPs.
The original ARM architecture wide cache_.h is changed to dummy version
for targets not implementing/enablig cache at all.
The ARM targets equipped by cache should include
appropriate implementation.
Next options are available for now
c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
basic ARM cache integrated on the CPU core directly
which requires only CP15 oparations
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
support for case where ARM L2C-310 cache controller
is used. It is accessible as mmaped peripheral.
c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
Cortex-M specific cache support
Updates #2782
Updates #2783
Diffstat (limited to 'depcomp')
0 files changed, 0 insertions, 0 deletions