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authorSebastian Huber <sebastian.huber@embedded-brains.de>2021-06-24 12:20:32 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2021-06-29 14:53:42 +0200
commitbb9a4b816b7efaab4e1e45e4c1ea1d81f6c8a21e (patch)
tree2733c644b6e3641aa214053e1f4252244b067052 /cpukit
parent9b84adb4aa7bfbd39cf8417863eae559426bfedb (diff)
downloadrtems-bb9a4b816b7efaab4e1e45e4c1ea1d81f6c8a21e.tar.bz2
arm: For AArch32 use non-shareable memory
The Cortex-R52 does not support cache coherency and the shareable memory attribute. If a region is configured to be shareable, then it falls back to use non-cacheable memory. Update #4202.
Diffstat (limited to 'cpukit')
-rw-r--r--cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h b/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h
index 825a057b03..a12bf994f1 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h
@@ -141,7 +141,7 @@ extern "C" {
( AARCH32_PMSA_ATTR_EN | \
AARCH32_PMSA_ATTR_XN | \
AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_NO ) | \
- AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_OUTER ) | \
+ AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \
AARCH32_PMSA_ATTR_IDX( 0U ) )
#define AARCH32_PMSA_DATA_READ_ONLY_UNCACHED \
@@ -155,7 +155,7 @@ extern "C" {
( AARCH32_PMSA_ATTR_EN | \
AARCH32_PMSA_ATTR_XN | \
AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO | \
- AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_OUTER ) | \
+ AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \
AARCH32_PMSA_ATTR_IDX( 0U ) )
#define AARCH32_PMSA_DATA_READ_WRITE_UNCACHED \