bsps/riscv: Add Microchip PolarFire SoC BSP variant

The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.

2 files changed, 2 insertions, 2 deletions

diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index f0f3da05da..88f7e7960c 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -481,7 +481,7 @@ static inline uint32_t _CPU_SMP_Get_current_processor( void )
     "=&r" ( mhartid )
   );
 
-  return (uint32_t) mhartid;
+  return (uint32_t) mhartid - RISCV_BOOT_HARTID;
 }
 
 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
index c38d21495a..5fd25e32cf 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
@@ -325,7 +325,7 @@ typedef struct {
   uint32_t priority[RISCV_PLIC_MAX_INTERRUPTS];
   uint32_t pending[1024];
   uint32_t enable[16320][32];
-  RISCV_PLIC_hart_regs harts[CPU_MAXIMUM_PROCESSORS];
+  RISCV_PLIC_hart_regs harts[CPU_MAXIMUM_PROCESSORS + RISCV_BOOT_HARTID];
 } RISCV_PLIC_regs;
 
 typedef struct {