score: Rename _ISR_Disable() and _ISR_Enable()

Rename _ISR_Disable() into _ISR_Local_disable().  Rename _ISR_Enable()
into _ISR_Local_enable().  Remove _Debug_Is_owner_of_giant().

This is a preparation to remove the Giant lock.

Update #2555.

14 files changed, 69 insertions, 105 deletions

diff --git a/cpukit/rtems/include/rtems/rtems/intr.h b/cpukit/rtems/include/rtems/rtems/intr.h
index ebf7a58f0c..4142230b31 100644
--- a/cpukit/rtems/include/rtems/rtems/intr.h
+++ b/cpukit/rtems/include/rtems/rtems/intr.h
@@ -100,7 +100,7 @@ rtems_status_code rtems_interrupt_catch(
  *  rtems_interrupt_local_disable() is available on all configurations.
  */
 #define rtems_interrupt_disable( _isr_cookie ) \
-    _ISR_Disable(_isr_cookie)
+    _ISR_Local_disable(_isr_cookie)
 
 /**
  *  @brief Enable RTEMS Interrupt
@@ -111,7 +111,7 @@ rtems_status_code rtems_interrupt_catch(
  *  rtems_interrupt_local_enable() is available on all configurations.
  */
 #define rtems_interrupt_enable( _isr_cookie ) \
-    _ISR_Enable(_isr_cookie)
+    _ISR_Local_enable(_isr_cookie)
 
 /**
  *  @brief Flash RTEMS Interrupt
diff --git a/cpukit/rtems/src/intrbody.c b/cpukit/rtems/src/intrbody.c
index a82dc101e6..abee60d5b7 100644
--- a/cpukit/rtems/src/intrbody.c
+++ b/cpukit/rtems/src/intrbody.c
@@ -47,7 +47,7 @@ rtems_interrupt_level rtems_interrupt_disable( void )
 {
   rtems_interrupt_level previous_level;
 
-  _ISR_Disable( previous_level );
+  _ISR_Local_disable( previous_level );
 
   return previous_level;
 }
@@ -56,7 +56,7 @@ void rtems_interrupt_enable(
   rtems_interrupt_level previous_level
 )
 {
-  _ISR_Enable( previous_level );
+  _ISR_Local_enable( previous_level );
 }
 
 void rtems_interrupt_flash(
diff --git a/cpukit/score/cpu/arm/armv7m-isr-vector-install.c b/cpukit/score/cpu/arm/armv7m-isr-vector-install.c
index ca3eeb3590..cb3abc91a9 100644
--- a/cpukit/score/cpu/arm/armv7m-isr-vector-install.c
+++ b/cpukit/score/cpu/arm/armv7m-isr-vector-install.c
@@ -35,12 +35,12 @@ void _CPU_ISR_install_vector(
 {
   uint32_t level;
 
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   if ( old_handler != NULL ) {
     *old_handler = _ARMV7M_Get_exception_handler( (int) vector );
   }
   _ARMV7M_Set_exception_handler( (int) vector, new_handler );
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 }
 
 #endif /* ARM_MULTILIB_ARCH_V7M */
diff --git a/cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c b/cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c
index a8e39df9c7..05602cd257 100644
--- a/cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c
+++ b/cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c
@@ -30,9 +30,9 @@ uint32_t _Nios2_MPU_Disable_protected( void )
   ISR_Level level;
   uint32_t config;
 
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   config = _Nios2_MPU_Disable();
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return config;
 }
diff --git a/cpukit/score/cpu/or1k/cpu.c b/cpukit/score/cpu/or1k/cpu.c
index 3cf6f6ba81..fe933f0cbb 100644
--- a/cpukit/score/cpu/or1k/cpu.c
+++ b/cpukit/score/cpu/or1k/cpu.c
@@ -88,7 +88,7 @@ void _CPU_ISR_install_vector(
 
    ISR_Level level;
 
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
 
   current_handler = table [vector];
 
@@ -102,7 +102,7 @@ void _CPU_ISR_install_vector(
     table [vector] = new_handler;
   }
 
-   _ISR_Enable( level );
+   _ISR_Local_enable( level );
 }
 
 void _CPU_Install_interrupt_stack( void )
diff --git a/cpukit/score/include/rtems/score/assert.h b/cpukit/score/include/rtems/score/assert.h
index 69736ae70e..c61c0a0399 100644
--- a/cpukit/score/include/rtems/score/assert.h
+++ b/cpukit/score/include/rtems/score/assert.h
@@ -95,24 +95,13 @@ extern "C" {
  * @brief Returns true if thread dispatching is allowed.
  *
  * Thread dispatching can be repressed via _Thread_Disable_dispatch() or
- * _ISR_Disable().
+ * _ISR_Local_disable().
  */
 #if defined( RTEMS_DEBUG )
   bool _Debug_Is_thread_dispatching_allowed( void );
 #endif
 
 /**
- * @brief Returns true if the current thread of execution owns the giant lock.
- */
-#if defined( RTEMS_DEBUG )
-  #if defined( RTEMS_SMP )
-    bool _Debug_Is_owner_of_giant( void );
-  #else
-    #define _Debug_Is_owner_of_giant() (true)
-  #endif
-#endif
-
-/**
  * @brief Returns true if the current thread of execution owns the allocator
  * mutex.
  */
diff --git a/cpukit/score/include/rtems/score/cpustdatomic.h b/cpukit/score/include/rtems/score/cpustdatomic.h
index fb7ba2d89c..6c6db8d279 100644
--- a/cpukit/score/include/rtems/score/cpustdatomic.h
+++ b/cpukit/score/include/rtems/score/cpustdatomic.h
@@ -277,10 +277,10 @@ static inline unsigned int _CPU_atomic_Fetch_add_uint( CPU_atomic_Uint *obj, uns
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   val = *obj;
   *obj = val + arg;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return val;
 #endif
@@ -297,10 +297,10 @@ static inline unsigned long _CPU_atomic_Fetch_add_ulong( CPU_atomic_Ulong *obj,
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   val = *obj;
   *obj = val + arg;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return val;
 #endif
@@ -317,10 +317,10 @@ static inline uintptr_t _CPU_atomic_Fetch_add_uintptr( CPU_atomic_Uintptr *obj,
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   val = *obj;
   *obj = val + arg;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return val;
 #endif
@@ -337,10 +337,10 @@ static inline unsigned int _CPU_atomic_Fetch_sub_uint( CPU_atomic_Uint *obj, uns
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   val = *obj;
   *obj = val - arg;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return val;
 #endif
@@ -357,10 +357,10 @@ static inline unsigned long _CPU_atomic_Fetch_sub_ulong( CPU_atomic_Ulong *obj,
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   val = *obj;
   *obj = val - arg;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return val;
 #endif
@@ -377,10 +377,10 @@ static inline uintptr_t _CPU_atomic_Fetch_sub_uintptr( CPU_atomic_Uintptr *obj,
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   val = *obj;
   *obj = val - arg;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return val;
 #endif
@@ -397,10 +397,10 @@ static inline unsigned int _CPU_atomic_Fetch_or_uint( CPU_atomic_Uint *obj, unsi
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   val = *obj;
   *obj = val | arg;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return val;
 #endif
@@ -417,10 +417,10 @@ static inline unsigned long _CPU_atomic_Fetch_or_ulong( CPU_atomic_Ulong *obj, u
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   val = *obj;
   *obj = val | arg;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return val;
 #endif
@@ -437,10 +437,10 @@ static inline uintptr_t _CPU_atomic_Fetch_or_uintptr( CPU_atomic_Uintptr *obj, u
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   val = *obj;
   *obj = val | arg;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return val;
 #endif
@@ -457,10 +457,10 @@ static inline unsigned int _CPU_atomic_Fetch_and_uint( CPU_atomic_Uint *obj, uns
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   val = *obj;
   *obj = val & arg;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return val;
 #endif
@@ -477,10 +477,10 @@ static inline unsigned long _CPU_atomic_Fetch_and_ulong( CPU_atomic_Ulong *obj,
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   val = *obj;
   *obj = val & arg;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return val;
 #endif
@@ -497,10 +497,10 @@ static inline uintptr_t _CPU_atomic_Fetch_and_uintptr( CPU_atomic_Uintptr *obj,
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   val = *obj;
   *obj = val & arg;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return val;
 #endif
@@ -517,10 +517,10 @@ static inline unsigned int _CPU_atomic_Exchange_uint( CPU_atomic_Uint *obj, unsi
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   val = *obj;
   *obj = desired;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return val;
 #endif
@@ -537,10 +537,10 @@ static inline unsigned long _CPU_atomic_Exchange_ulong( CPU_atomic_Ulong *obj, u
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   val = *obj;
   *obj = desired;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return val;
 #endif
@@ -557,10 +557,10 @@ static inline uintptr_t _CPU_atomic_Exchange_uintptr( CPU_atomic_Uintptr *obj, u
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   val = *obj;
   *obj = desired;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return val;
 #endif
@@ -579,7 +579,7 @@ static inline bool _CPU_atomic_Compare_exchange_uint( CPU_atomic_Uint *obj, unsi
 
   (void) succ;
   (void) fail;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   actual = *obj;
   success = ( actual == *expected );
   if ( success ) {
@@ -587,7 +587,7 @@ static inline bool _CPU_atomic_Compare_exchange_uint( CPU_atomic_Uint *obj, unsi
   } else {
     *expected = actual;
   }
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return success;
 #endif
@@ -606,7 +606,7 @@ static inline bool _CPU_atomic_Compare_exchange_ulong( CPU_atomic_Ulong *obj, un
 
   (void) succ;
   (void) fail;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   actual = *obj;
   success = ( actual == *expected );
   if ( success ) {
@@ -614,7 +614,7 @@ static inline bool _CPU_atomic_Compare_exchange_ulong( CPU_atomic_Ulong *obj, un
   } else {
     *expected = actual;
   }
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return success;
 #endif
@@ -633,7 +633,7 @@ static inline bool _CPU_atomic_Compare_exchange_uintptr( CPU_atomic_Uintptr *obj
 
   (void) succ;
   (void) fail;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   actual = *obj;
   success = ( actual == *expected );
   if ( success ) {
@@ -641,7 +641,7 @@ static inline bool _CPU_atomic_Compare_exchange_uintptr( CPU_atomic_Uintptr *obj
   } else {
     *expected = actual;
   }
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return success;
 #endif
@@ -670,10 +670,10 @@ static inline bool _CPU_atomic_Flag_test_and_set( CPU_atomic_Flag *obj, CPU_atom
   ISR_Level level;
 
   (void) order;
-  _ISR_Disable( level );
+  _ISR_Local_disable( level );
   flag = *obj;
   *obj = true;
-  _ISR_Enable( level );
+  _ISR_Local_enable( level );
 
   return flag;
 #endif
diff --git a/cpukit/score/include/rtems/score/isrlevel.h b/cpukit/score/include/rtems/score/isrlevel.h
index cf8712a967..0eccd3aea1 100644
--- a/cpukit/score/include/rtems/score/isrlevel.h
+++ b/cpukit/score/include/rtems/score/isrlevel.h
@@ -55,10 +55,9 @@ typedef uint32_t   ISR_Level;
  *  @param[out] _level The argument @a _level will contain the previous
  *  interrupt mask level.
  */
-#define _ISR_Disable( _level ) \
+#define _ISR_Local_disable( _level ) \
   do { \
     _CPU_ISR_Disable( _level ); \
-    _Assert( _Debug_Is_owner_of_giant() ); \
     RTEMS_COMPILER_MEMORY_BARRIER(); \
   } while (0)
 
@@ -66,17 +65,16 @@ typedef uint32_t   ISR_Level;
  *  @brief Enables interrupts on this processor.
  *
  *  This macro restores the interrupt status on the processor with the
- *  interrupt level value obtained by _ISR_Disable().  It is used at the end of
+ *  interrupt level value obtained by _ISR_Local_disable().  It is used at the end of
  *  a critical section of code to enable interrupts so they can be processed
  *  again.
  *
  *  @param[in] _level The interrupt level previously obtained by
- *  _ISR_Disable().
+ *  _ISR_Local_disable().
  */
-#define _ISR_Enable( _level ) \
+#define _ISR_Local_enable( _level ) \
   do { \
     RTEMS_COMPILER_MEMORY_BARRIER(); \
-    _Assert( _Debug_Is_owner_of_giant() ); \
     _CPU_ISR_Enable( _level ); \
   } while (0)
 
@@ -97,12 +95,11 @@ typedef uint32_t   ISR_Level;
  *  properly protects itself.
  *
  *  @param[in] _level The interrupt level previously obtained by
- *  _ISR_Disable().
+ *  _ISR_Local_disable().
  */
 #define _ISR_Flash( _level ) \
   do { \
     RTEMS_COMPILER_MEMORY_BARRIER(); \
-    _Assert( _Debug_Is_owner_of_giant() ); \
     _CPU_ISR_Flash( _level ); \
     RTEMS_COMPILER_MEMORY_BARRIER(); \
   } while (0)
@@ -136,18 +133,6 @@ typedef uint32_t   ISR_Level;
     RTEMS_COMPILER_MEMORY_BARRIER();  \
   } while (0)
 
-#define _ISR_Local_disable( _level ) \
-  do { \
-    _CPU_ISR_Disable( _level ); \
-    RTEMS_COMPILER_MEMORY_BARRIER(); \
-  } while (0)
-
-#define _ISR_Local_enable( _level ) \
-  do { \
-    RTEMS_COMPILER_MEMORY_BARRIER(); \
-    _CPU_ISR_Enable( _level ); \
-  } while (0)
-
 /**@}*/
 
 #ifdef __cplusplus
diff --git a/cpukit/score/include/rtems/score/isrlock.h b/cpukit/score/include/rtems/score/isrlock.h
index 2af75c94cd..3843fd6454 100644
--- a/cpukit/score/include/rtems/score/isrlock.h
+++ b/cpukit/score/include/rtems/score/isrlock.h
@@ -203,7 +203,7 @@ typedef struct {
     )
 #else
   #define _ISR_lock_ISR_disable_and_acquire( _lock, _context ) \
-    _ISR_Disable( ( _context )->isr_level )
+    _ISR_Local_disable( ( _context )->isr_level )
 #endif
 
 /**
@@ -228,7 +228,7 @@ typedef struct {
     )
 #else
   #define _ISR_lock_Release_and_ISR_enable( _lock, _context ) \
-    _ISR_Enable( ( _context )->isr_level )
+    _ISR_Local_enable( ( _context )->isr_level )
 #endif
 
 /**
@@ -357,7 +357,7 @@ typedef struct {
 #else
   #define _ISR_lock_ISR_disable( _context ) \
     do { \
-      _ISR_Disable( ( _context )->isr_level ); \
+      _ISR_Local_disable( ( _context )->isr_level ); \
       _ISR_lock_ISR_disable_profile( _context ) \
     } while ( 0 )
 #endif
@@ -377,7 +377,7 @@ typedef struct {
     _ISR_Local_enable( ( _context )->Lock_context.isr_level )
 #else
   #define _ISR_lock_ISR_enable( _context ) \
-    _ISR_Enable( ( _context )->isr_level )
+    _ISR_Local_enable( ( _context )->isr_level )
 #endif
 
 /** @} */
diff --git a/cpukit/score/include/rtems/score/percpu.h b/cpukit/score/include/rtems/score/percpu.h
index fa0c289f31..ea69cd6c2b 100644
--- a/cpukit/score/include/rtems/score/percpu.h
+++ b/cpukit/score/include/rtems/score/percpu.h
@@ -499,7 +499,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT;
 #else
 #define _Per_CPU_ISR_disable_and_acquire( cpu, isr_cookie ) \
   do { \
-    _ISR_Disable( isr_cookie ); \
+    _ISR_Local_disable( isr_cookie ); \
     (void) ( cpu ); \
   } while ( 0 )
 #endif
@@ -514,7 +514,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT;
 #define _Per_CPU_Release_and_ISR_enable( cpu, isr_cookie ) \
   do { \
     (void) ( cpu ); \
-    _ISR_Enable( isr_cookie ); \
+    _ISR_Local_enable( isr_cookie ); \
   } while ( 0 )
 #endif
 
@@ -530,7 +530,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT;
   } while ( 0 )
 #else
 #define _Per_CPU_Acquire_all( isr_cookie ) \
-  _ISR_Disable( isr_cookie )
+  _ISR_Local_disable( isr_cookie )
 #endif
 
 #if defined( RTEMS_SMP )
@@ -545,7 +545,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT;
   } while ( 0 )
 #else
 #define _Per_CPU_Release_all( isr_cookie ) \
-  _ISR_Enable( isr_cookie )
+  _ISR_Local_enable( isr_cookie )
 #endif
 
 /*
diff --git a/cpukit/score/include/rtems/score/threaddispatch.h b/cpukit/score/include/rtems/score/threaddispatch.h
index ac8855b76c..be3883ffbc 100644
--- a/cpukit/score/include/rtems/score/threaddispatch.h
+++ b/cpukit/score/include/rtems/score/threaddispatch.h
@@ -152,7 +152,7 @@ RTEMS_INLINE_ROUTINE void _Thread_Dispatch_initialization( void )
 #if defined( RTEMS_PROFILING )
     ISR_Level level;
 
-    _ISR_Disable( level );
+    _ISR_Local_disable( level );
     _Profiling_Thread_dispatch_disable( _Per_CPU_Get(), disable_level );
 #endif
 
@@ -160,7 +160,7 @@ RTEMS_INLINE_ROUTINE void _Thread_Dispatch_initialization( void )
     _Thread_Dispatch_disable_level = disable_level;
 
 #if defined( RTEMS_PROFILING )
-    _ISR_Enable( level );
+    _ISR_Local_enable( level );
 #endif
 
     return disable_level;
@@ -177,7 +177,7 @@ RTEMS_INLINE_ROUTINE void _Thread_Dispatch_initialization( void )
 #if defined( RTEMS_PROFILING )
     ISR_Level level;
 
-    _ISR_Disable( level );
+    _ISR_Local_disable( level );
 #endif
 
     --disable_level;
@@ -185,7 +185,7 @@ RTEMS_INLINE_ROUTINE void _Thread_Dispatch_initialization( void )
 
 #if defined( RTEMS_PROFILING )
     _Profiling_Thread_dispatch_enable( _Per_CPU_Get(), disable_level );
-    _ISR_Enable( level );
+    _ISR_Local_enable( level );
 #endif
 
     return disable_level;
diff --git a/cpukit/score/include/rtems/score/threadimpl.h b/cpukit/score/include/rtems/score/threadimpl.h
index 73f9c9a2a9..ce31457c2a 100644
--- a/cpukit/score/include/rtems/score/threadimpl.h
+++ b/cpukit/score/include/rtems/score/threadimpl.h
@@ -1166,7 +1166,7 @@ RTEMS_INLINE_ROUTINE void *_Thread_Lock_acquire(
     _Thread_Lock_release( lock, lock_context );
   }
 #else
-  _ISR_Disable( lock_context->isr_level );
+  _ISR_Local_disable( lock_context->isr_level );
 
   return NULL;
 #endif
diff --git a/cpukit/score/src/threaddispatch.c b/cpukit/score/src/threaddispatch.c
index 4d840bfded..5a9c5669c1 100644
--- a/cpukit/score/src/threaddispatch.c
+++ b/cpukit/score/src/threaddispatch.c
@@ -104,7 +104,7 @@ void _Thread_Do_dispatch( Per_CPU_Control *cpu_self, ISR_Level level )
      * to this function.
      */
 #if !defined( RTEMS_SMP )
-    _ISR_Enable( level );
+    _ISR_Local_enable( level );
 #endif
 
     _User_extensions_Thread_switch( executing, heir );
@@ -122,7 +122,7 @@ void _Thread_Do_dispatch( Per_CPU_Control *cpu_self, ISR_Level level )
     _Thread_Debug_set_real_processor( executing, cpu_self );
 
 #if !defined( RTEMS_SMP )
-    _ISR_Disable( level );
+    _ISR_Local_disable( level );
 #endif
   } while (
 #if defined( RTEMS_SMP )
diff --git a/cpukit/score/src/threaddispatchdisablelevel.c b/cpukit/score/src/threaddispatchdisablelevel.c
index 826d5b25b5..75b12bd358 100644
--- a/cpukit/score/src/threaddispatchdisablelevel.c
+++ b/cpukit/score/src/threaddispatchdisablelevel.c
@@ -138,13 +138,3 @@ void _Giant_Release( Per_CPU_Control *cpu_self )
   _Giant_Do_release( cpu_self );
   _ISR_Local_enable( isr_level );
 }
-
-#if defined( RTEMS_DEBUG )
-bool _Debug_Is_owner_of_giant( void )
-{
-  Giant_Control *giant = &_Giant;
-
-  return giant->owner_cpu == _Per_CPU_Get_snapshot()
-    || !_System_state_Is_up( _System_state_Get() );
-}
-#endif