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| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-07-02 14:33:11 +0200 |
|---|---|---|
| committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-10-02 10:40:33 +0200 |
| commit | 9aaf8f2b0b3fb4b95b1a635714c13091c30e00e2 (patch) | |
| tree | 1cc24132f77ff0b5be1b0742c998365db774cd32 /cpukit | |
| parent | arm/score and shared: define ARM hypervisor mode and alternate vector table b... (diff) | |
| download | rtems-9aaf8f2b0b3fb4b95b1a635714c13091c30e00e2.tar.bz2 | |
score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib.
Some/many Cortex-A cores have data cache line length 64 bytes and maximum
value has to be used for system structures alignment.
Updates #2782
Updates #2783
Diffstat (limited to 'cpukit')
| -rw-r--r-- | cpukit/score/cpu/arm/rtems/score/arm.h | 4 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/rtems/score/cpu.h | 9 |
2 files changed, 11 insertions, 2 deletions
diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h b/cpukit/score/cpu/arm/rtems/score/arm.h index 6d1f8502a3..af32fc3150 100644 --- a/cpukit/score/cpu/arm/rtems/score/arm.h +++ b/cpukit/score/cpu/arm/rtems/score/arm.h @@ -53,6 +53,10 @@ extern "C" { #define ARM_MULTILIB_HAS_THREAD_ID_REGISTER #endif +#if defined(__ARM_ARCH_7A__) + #define ARM_MULTILIB_CACHE_LINE_MAX_64 +#endif + #if !defined(__SOFTFP__) #if defined(__ARM_NEON__) #define ARM_MULTILIB_VFP_D32 diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h index 9dc4d07103..25d4ee2fb7 100644 --- a/cpukit/score/cpu/arm/rtems/score/cpu.h +++ b/cpukit/score/cpu/arm/rtems/score/cpu.h @@ -145,8 +145,13 @@ #define CPU_STACK_GROWS_UP FALSE -/* XXX Why 32? */ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) +#if defined(ARM_MULTILIB_CACHE_LINE_MAX_64) + #define CPU_CACHE_LINE_BYTES 32 +#else + #define CPU_CACHE_LINE_BYTES 64 +#endif + +#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (CPU_CACHE_LINE_BYTES ))) #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE |