bsp/csb336: Memory map update to support i.MX1 based PiMX1 as well.

CSB336 i.MX1/i.MXS memory map organization

 - SDRAM starts at address 0x08000000 but 2 MB are reserved
   for boot-block/loader (or other use) before RTEMS image
   origin/load address (that is kept from previous setup)

 - Caching of 30 MB of SDRAM used for RTEMS (start at 0x08200000)
   is changed to writeback mode which provides higher throughput.

 - The first 1 MB of RTEMS dedicated SDRAM is remapped to address 0
   to provide area for ARM CPU exceptions table.

 - Internal registers and rest of the Flash (above 1 MB) are mapped
   one to one. Registers region is extended to 2 MB to cover
   eSRAM found on i.MX1 chip variant.

 - The first two megabytes of SDRAM unused by RTEMS are mapped
   with attributes to allow specific purposes.

   - the first MB (at address 0x08000000) is nocached to allow
     directly set some values read by booot-block after warm reset

   - the second MB (at address 0x08100000) is set for write-through
     caching.  That allows to use memory for LCD frame-buffer without
     need to flush cache after each redraw.

Signed-off-by: Pavel Pisa <pi@baree.pikron.com>

0 files changed, 0 insertions, 0 deletions