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authorAlex White <alex.white@oarcorp.com>2021-01-11 10:23:16 -0600
committerJoel Sherrill <joel@rtems.org>2021-03-05 08:43:15 -0600
commit9aff7e5685164f062b34d24e1002b7137d6f8496 (patch)
tree5628a80443c605111af28e7f02297182a737207b /cpukit/score
parentcpukit: Explicitly enforce alignment requirements (diff)
downloadrtems-9aff7e5685164f062b34d24e1002b7137d6f8496.tar.bz2
score/aarch64: Fix interrupt level reads
Diffstat (limited to 'cpukit/score')
-rw-r--r--cpukit/score/cpu/aarch64/cpu.c2
-rw-r--r--cpukit/score/cpu/aarch64/include/rtems/score/cpu.h8
2 files changed, 7 insertions, 3 deletions
diff --git a/cpukit/score/cpu/aarch64/cpu.c b/cpukit/score/cpu/aarch64/cpu.c
index b977875fc3..75b1125cf7 100644
--- a/cpukit/score/cpu/aarch64/cpu.c
+++ b/cpukit/score/cpu/aarch64/cpu.c
@@ -166,7 +166,7 @@ uint64_t _CPU_ISR_Get_level( void )
: [level] "=&r" (level)
);
- return level & AARCH64_PSTATE_I;
+ return ( level & AARCH64_PSTATE_I ) != 0;
}
void _CPU_ISR_install_vector(
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
index 380d1380fb..ceb831a43f 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
@@ -215,10 +215,14 @@ void AArch64_interrupt_flash( uint64_t level );
#else
static inline uint64_t AArch64_interrupt_disable( void )
{
- uint64_t level = _CPU_ISR_Get_level();
+ uint64_t level;
+
__asm__ volatile (
+ "mrs %[level], DAIF\n"
"msr DAIFSet, #0x2\n"
+ : [level] "=&r" (level)
);
+
return level;
}
@@ -250,7 +254,7 @@ static inline void AArch64_interrupt_flash( uint64_t level )
RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint64_t level )
{
- return ( level & AARCH64_PSTATE_I ) == 0;
+ return level == 0;
}
void _CPU_Context_Initialize(