score: Add CPU_THREAD_LOCAL_STORAGE_VARIANT

Update #3835.

38 files changed, 122 insertions, 63 deletions

diff --git a/cpukit/score/cpu/aarch64/cpu.c b/cpukit/score/cpu/aarch64/cpu.c
index 923f53da08..207508302b 100644
--- a/cpukit/score/cpu/aarch64/cpu.c
+++ b/cpukit/score/cpu/aarch64/cpu.c
@@ -142,7 +142,7 @@ void _CPU_Context_Initialize(
   the_context->thread_id = (uintptr_t) tls_area;
 
   if ( tls_area != NULL ) {
-    _TLS_TCB_at_area_begin_initialize( tls_area );
+    the_context->thread_id = (uintptr_t) _TLS_Initialize_area( tls_area );
   }
 }
 
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
index 880ae7d9f7..b520e8bffb 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
@@ -50,8 +50,11 @@
  */
 
 #define CPU_PER_CPU_CONTROL_SIZE 0
+
 #define CPU_INTERRUPT_FRAME_SIZE 0x2E0
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 11
+
 #ifndef ASM
 
 #ifdef __cplusplus
diff --git a/cpukit/score/cpu/arm/__aeabi_read_tp.c b/cpukit/score/cpu/arm/__aeabi_read_tp.c
index 671065825d..8ae218bbcb 100644
--- a/cpukit/score/cpu/arm/__aeabi_read_tp.c
+++ b/cpukit/score/cpu/arm/__aeabi_read_tp.c
@@ -42,15 +42,15 @@ void __attribute__((naked)) __aeabi_read_tp(void)
     "ldr r0, =_Per_CPU_Information\n"
     "ldr r0, [r0, %[executingoff]]\n"
 #if defined(__thumb__) && !defined(__thumb2__)
-    "add r0, %[tlsareaoff]\n"
+    "add r0, %[threadidoff]\n"
     "ldr r0, [r0]\n"
 #else
-    "ldr r0, [r0, %[tlsareaoff]]\n"
+    "ldr r0, [r0, %[threadidoff]]\n"
 #endif
     "bx lr\n"
     :
     : [executingoff] "I" (offsetof(Per_CPU_Control, executing)),
-      [tlsareaoff] "I" (offsetof(Thread_Control, Start.tls_area))
+      [threadidoff] "I" (offsetof(Thread_Control, Registers.thread_id))
   );
 }
 
diff --git a/cpukit/score/cpu/arm/__tls_get_addr.c b/cpukit/score/cpu/arm/__tls_get_addr.c
index 5c8e60ae06..d75ddf93de 100644
--- a/cpukit/score/cpu/arm/__tls_get_addr.c
+++ b/cpukit/score/cpu/arm/__tls_get_addr.c
@@ -39,10 +39,10 @@ void *__tls_get_addr(const TLS_Index *ti);
 void *__tls_get_addr(const TLS_Index *ti)
 {
   const Thread_Control *executing = _Thread_Get_executing();
-  void *tls_block = (char *) executing->Start.tls_area
-    + _TLS_Get_thread_control_block_area_size( (uintptr_t) _TLS_Alignment );
+  void *tls_data = (char *) executing->Registers.thread_id
+    + _TLS_Get_thread_control_block_area_size();
 
   assert(ti->module == 1);
 
-  return (char *) tls_block + ti->offset;
+  return (char *) tls_data + ti->offset;
 }
diff --git a/cpukit/score/cpu/arm/armv7m-context-initialize.c b/cpukit/score/cpu/arm/armv7m-context-initialize.c
index 6bdedecb77..58c7269193 100644
--- a/cpukit/score/cpu/arm/armv7m-context-initialize.c
+++ b/cpukit/score/cpu/arm/armv7m-context-initialize.c
@@ -61,7 +61,7 @@ void _CPU_Context_Initialize(
   context->register_sp = stack_area_end;
 
   if ( tls_area != NULL ) {
-    _TLS_TCB_at_area_begin_initialize( tls_area );
+    _TLS_Initialize_area( tls_area );
   }
 }
 
diff --git a/cpukit/score/cpu/arm/cpu.c b/cpukit/score/cpu/arm/cpu.c
index b2cc6039b0..b685c4d6ab 100644
--- a/cpukit/score/cpu/arm/cpu.c
+++ b/cpukit/score/cpu/arm/cpu.c
@@ -56,13 +56,11 @@
   );
 #endif
 
-#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
-  RTEMS_STATIC_ASSERT(
-    offsetof( Context_Control, thread_id )
-      == ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET,
-    ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET
-  );
-#endif
+RTEMS_STATIC_ASSERT(
+  offsetof( Context_Control, thread_id )
+    == ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET,
+  ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET
+);
 
 #ifdef ARM_MULTILIB_ARCH_V4
   RTEMS_STATIC_ASSERT(
@@ -118,13 +116,10 @@ void _CPU_Context_Initialize(
   the_context->register_sp = (uint32_t) stack_area_begin + stack_area_size;
   the_context->register_lr = (uint32_t) entry_point;
   the_context->isr_dispatch_disable = 0;
-
-#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
   the_context->thread_id = (uint32_t) tls_area;
-#endif
 
   if ( tls_area != NULL ) {
-    _TLS_TCB_at_area_begin_initialize( tls_area );
+    the_context->thread_id = (uint32_t) _TLS_Initialize_area( tls_area );
   }
 }
 
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
index beb917a0b7..70b53ded62 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
@@ -176,9 +176,7 @@
 
 #define CPU_MAXIMUM_PROCESSORS 32
 
-#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
-  #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44
-#endif
+#define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44
 
 #ifdef ARM_MULTILIB_VFP
   #define ARM_CONTEXT_CONTROL_D8_OFFSET 48
@@ -191,10 +189,8 @@
 #ifdef RTEMS_SMP
   #if defined(ARM_MULTILIB_VFP)
     #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112
-  #elif defined(ARM_MULTILIB_HAS_THREAD_ID_REGISTER)
-    #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48
   #else
-    #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 44
+    #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48
   #endif
 #endif
 
@@ -240,9 +236,7 @@ typedef struct {
 #else
   void *register_sp;
 #endif
-#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
   uint32_t thread_id;
-#endif
 #ifdef ARM_MULTILIB_VFP
   uint64_t register_d8;
   uint64_t register_d9;
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
index 6e8230ce30..56eccf2e6f 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
@@ -60,6 +60,8 @@
 
 #endif /* ARM_MULTILIB_ARCH_V4 */
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 11
+
 #ifndef ASM
 
 #ifdef __cplusplus
diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
index a03bc596ba..695963858a 100644
--- a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
@@ -29,6 +29,8 @@
 
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
 #ifndef ASM
 
 #ifdef __cplusplus
diff --git a/cpukit/score/cpu/i386/cpu.c b/cpukit/score/cpu/i386/cpu.c
index e89cdebdbe..9a3b188d10 100644
--- a/cpukit/score/cpu/i386/cpu.c
+++ b/cpukit/score/cpu/i386/cpu.c
@@ -193,7 +193,7 @@ void _CPU_Context_Initialize(
   the_context->esp     = (void *) _stack;
 
   if ( tls_area != NULL ) {
-    tcb = (uint32_t) _TLS_TCB_after_TLS_block_initialize( tls_area );
+    tcb = (uint32_t) _TLS_Initialize_area( tls_area );
   } else {
     tcb = 0;
   }
diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
index 4f99f64711..6f67fa2878 100644
--- a/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
@@ -50,6 +50,8 @@
 
 #define CPU_INTERRUPT_FRAME_SIZE 52
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 20
+
 #ifndef ASM
 
 #ifdef __cplusplus
diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
index dce0cc6017..c49012af1f 100644
--- a/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
@@ -28,6 +28,8 @@
 
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
 #ifndef ASM
 
 #ifdef __cplusplus
diff --git a/cpukit/score/cpu/m68k/__m68k_read_tp.c b/cpukit/score/cpu/m68k/__m68k_read_tp.c
index e15ac3fed3..43dd1d16ac 100644
--- a/cpukit/score/cpu/m68k/__m68k_read_tp.c
+++ b/cpukit/score/cpu/m68k/__m68k_read_tp.c
@@ -37,9 +37,7 @@ void __m68k_read_tp(void);
 void __m68k_read_tp(void)
 {
   const Thread_Control *executing = _Thread_Get_executing();
-  void *tp = (char *) executing->Start.tls_area +
-    _TLS_Get_thread_control_block_area_size((uintptr_t) _TLS_Alignment)
-    + 0x7000;
+  void *tp = executing->Registers.thread_pointer;
 
   __asm__ volatile (
     "move.l %0, %%a0"
diff --git a/cpukit/score/cpu/m68k/cpu.c b/cpukit/score/cpu/m68k/cpu.c
index 9f6fb9223e..44dc06cc91 100644
--- a/cpukit/score/cpu/m68k/cpu.c
+++ b/cpukit/score/cpu/m68k/cpu.c
@@ -279,6 +279,9 @@ void _CPU_Context_Initialize(
 #endif
 
   if ( tls_area != NULL ) {
-    _TLS_TCB_before_TLS_block_initialize( tls_area );
+    the_context->thread_pointer =
+      (char *) _TLS_Initialize_area( tls_area ) + 0x7000;
+  } else {
+    the_context->thread_pointer = NULL;
   }
 }
diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpu.h b/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
index 8fdcb8c15a..ae3194b9bb 100644
--- a/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m68k/include/rtems/score/cpu.h
@@ -145,6 +145,7 @@ typedef struct {
   #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
     uint8_t   fpu_dis;
   #endif
+  void       *thread_pointer;
 } Context_Control;
 
 #define _CPU_Context_Get_SP( _context ) \
diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
index b94c846bf2..f712433833 100644
--- a/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
@@ -48,6 +48,8 @@
 
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
 #ifndef ASM
 
 #ifdef __cplusplus
diff --git a/cpukit/score/cpu/microblaze/__tls_get_addr.c b/cpukit/score/cpu/microblaze/__tls_get_addr.c
index e779a63488..b7e7890013 100644
--- a/cpukit/score/cpu/microblaze/__tls_get_addr.c
+++ b/cpukit/score/cpu/microblaze/__tls_get_addr.c
@@ -46,9 +46,11 @@ void *__tls_get_addr( const TLS_Index *ti );
 
 void *__tls_get_addr( const TLS_Index *ti )
 {
-  const Thread_Control *executing = _Thread_Get_executing();
-  void *tls_block = (char *) executing->Start.tls_area
-    + _TLS_Get_thread_control_block_area_size( (uintptr_t) _TLS_Alignment );
+  const Thread_Control *executing;
 
-  return (char *) tls_block + ti->offset;
+  (void) ti;
+
+  executing = _Thread_Get_executing();
+
+  return executing->Registers.thread_pointer;
 }
diff --git a/cpukit/score/cpu/microblaze/cpu.c b/cpukit/score/cpu/microblaze/cpu.c
index 1e829a4714..823825d2b1 100644
--- a/cpukit/score/cpu/microblaze/cpu.c
+++ b/cpukit/score/cpu/microblaze/cpu.c
@@ -73,7 +73,7 @@ void _CPU_Context_Initialize(
   context->rmsr = msr;
 
   if ( tls_area != NULL ) {
-    _TLS_TCB_at_area_begin_initialize( tls_area );
+    context->thread_pointer = _TLS_Initialize_area( tls_area );
   }
 }
 
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
index 1325962f7c..3d865732d6 100644
--- a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
@@ -137,6 +137,7 @@ typedef struct {
   uint32_t r30;
   uint32_t r31;
   uint32_t rmsr;
+  void *thread_pointer;
 } Context_Control;
 
 /**
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
index 0b9e06cfa8..4e315e856d 100644
--- a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h
@@ -49,8 +49,11 @@
  */
 
 #define CPU_PER_CPU_CONTROL_SIZE 0
+
 #define CPU_INTERRUPT_FRAME_SIZE 56
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
 #define MICROBLAZE_INTERRUPT_FRAME_R3   0
 #define MICROBLAZE_INTERRUPT_FRAME_R4   4
 #define MICROBLAZE_INTERRUPT_FRAME_R5   8
diff --git a/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h
index cb4c925630..64be130906 100644
--- a/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h
@@ -48,6 +48,8 @@
 
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
 #ifndef ASM
 
 #ifdef __cplusplus
diff --git a/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h
index 9c6ae11d74..d009186bbc 100644
--- a/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h
@@ -48,6 +48,8 @@
 
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
 #ifndef ASM
 
 #ifdef __cplusplus
diff --git a/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h
index 56c2cb0108..f257cba55f 100644
--- a/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/nios2/include/rtems/score/cpuimpl.h
@@ -48,6 +48,8 @@
 
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
 #ifndef ASM
 
 #ifdef __cplusplus
diff --git a/cpukit/score/cpu/nios2/nios2-context-initialize.c b/cpukit/score/cpu/nios2/nios2-context-initialize.c
index fe458cc2ca..14a06374b4 100644
--- a/cpukit/score/cpu/nios2/nios2-context-initialize.c
+++ b/cpukit/score/cpu/nios2/nios2-context-initialize.c
@@ -90,9 +90,6 @@ void _CPU_Context_Initialize(
   }
 
   if ( tls_area != NULL ) {
-    context->r23 = (uintptr_t) tls_area +
-      _TLS_Get_thread_control_block_area_size( (uintptr_t) _TLS_Alignment ) +
-       0x7000;
-    _TLS_TCB_before_TLS_block_initialize( tls_area );
+    context->r23 = (uintptr_t) _TLS_Initialize_area( tls_area ) + 0x7000;
   }
 }
diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
index d5082383e8..72d223de24 100644
--- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
@@ -54,6 +54,24 @@
  */
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
+/**
+ * @brief Defines the thread-local storage (TLS) variant.
+ *
+ * Use one of the following values:
+ *
+ * 10: The architecture uses Variant I and the TLS offsets emitted by the
+ *     linker neglect the TCB (examples: nios2, m68k, microblaze, powerpc,
+ *     riscv).  The thread pointer directly references the thread-local data
+ *     area.
+ *
+ * 11: The architecture uses Variant I and the TLS offsets emitted by the
+ *     linker take the TCB into account (examples: arm, aarch64).
+ *     The thread pointer references the TCB.
+ *
+ * 20: The architecture uses Variant II (examples: i386, sparc).
+ */
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
 #ifndef ASM
 
 #ifdef __cplusplus
diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h
index 352f14589a..8fbf8ba547 100644
--- a/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h
@@ -48,6 +48,8 @@
 
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
 #ifndef ASM
 
 #ifdef __cplusplus
diff --git a/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h
index c81675b53d..fa223f9aa8 100644
--- a/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h
@@ -151,6 +151,8 @@
 
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
 #ifdef RTEMS_SMP
 
 /* Use SPRG0 for the per-CPU control of the current processor */
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
index 5fd25e32cf..627c48f94c 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
@@ -54,6 +54,8 @@
 #define CPU_PER_CPU_CONTROL_SIZE 16
 #endif
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
 #ifdef RTEMS_SMP
 #define RISCV_CONTEXT_IS_EXECUTING 0
 #endif
diff --git a/cpukit/score/cpu/riscv/riscv-context-initialize.c b/cpukit/score/cpu/riscv/riscv-context-initialize.c
index c6bd99ebbd..572dc3ede3 100644
--- a/cpukit/score/cpu/riscv/riscv-context-initialize.c
+++ b/cpukit/score/cpu/riscv/riscv-context-initialize.c
@@ -68,7 +68,7 @@ void _CPU_Context_Initialize(
   if ( tls_area != NULL ) {
     void *tls_block;
 
-    tls_block = _TLS_TCB_before_TLS_block_initialize( tls_area );
+    tls_block = _TLS_Initialize_area( tls_area );
     context->tp = (uintptr_t) tls_block;
   }
 }
diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h
index 295b01eeaa..1746d677c0 100644
--- a/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h
@@ -29,6 +29,8 @@
 
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
 #ifndef ASM
 
 #ifdef __cplusplus
diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c
index b910d96d8d..ca11229023 100644
--- a/cpukit/score/cpu/sparc/cpu.c
+++ b/cpukit/score/cpu/sparc/cpu.c
@@ -319,7 +319,7 @@ void _CPU_Context_Initialize(
   the_context->isr_dispatch_disable = 0;
 
   if ( tls_area != NULL ) {
-    void *tcb = _TLS_TCB_after_TLS_block_initialize( tls_area );
+    void *tcb = _TLS_Initialize_area( tls_area );
 
     the_context->g7 = (uintptr_t) tcb;
   }
diff --git a/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h
index e98a75cf32..7a97db7097 100644
--- a/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h
@@ -120,6 +120,8 @@
   #define CPU_PER_CPU_CONTROL_SIZE 0
 #endif
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 20
+
 #if ( SPARC_HAS_FPU == 1 )
   /**
    * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
diff --git a/cpukit/score/cpu/sparc64/cpu.c b/cpukit/score/cpu/sparc64/cpu.c
index c93b68a2cc..ae3b359876 100644
--- a/cpukit/score/cpu/sparc64/cpu.c
+++ b/cpukit/score/cpu/sparc64/cpu.c
@@ -132,7 +132,7 @@ void _CPU_Context_Initialize(
     the_context->isr_dispatch_disable = 0;
 
   if ( tls_area != NULL ) {
-    void *tcb = _TLS_TCB_after_TLS_block_initialize( tls_area );
+    void *tcb = _TLS_Initialize_area( tls_area );
 
     the_context->g7 = (uintptr_t) tcb;
   }
diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h
index 8df4c8814c..10fe696fab 100644
--- a/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h
@@ -48,6 +48,8 @@
 
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 20
+
 #ifndef ASM
 
 #ifdef __cplusplus
diff --git a/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h
index 4b0f78c845..df0b9bc9e9 100644
--- a/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h
@@ -48,6 +48,8 @@
 
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
 #ifndef ASM
 
 #ifdef __cplusplus
diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
index 742763c168..bee49ca124 100644
--- a/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
@@ -32,6 +32,8 @@
 
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 20
+
 #ifndef ASM
 
 #ifdef __cplusplus
diff --git a/cpukit/score/src/threadinitialize.c b/cpukit/score/src/threadinitialize.c
index 9b37206c6d..31698524a9 100644
--- a/cpukit/score/src/threadinitialize.c
+++ b/cpukit/score/src/threadinitialize.c
@@ -267,12 +267,8 @@ static bool _Thread_Try_initialize(
 
   /* Allocate thread-local storage (TLS) area in stack area */
   if ( tls_size > 0 ) {
-    uintptr_t tls_align;
-
     stack_end -= tls_size;
-    tls_align = (uintptr_t) _TLS_Alignment;
-    the_thread->Start.tls_area = (void *)
-      ( ( (uintptr_t) stack_end + tls_align - 1 ) & ~( tls_align - 1 ) );
+    the_thread->Start.tls_area = stack_end;
   }
 
   _Stack_Initialize(
diff --git a/cpukit/score/src/tlsallocsize.c b/cpukit/score/src/tlsallocsize.c
index d761f3b6cf..1a4027d517 100644
--- a/cpukit/score/src/tlsallocsize.c
+++ b/cpukit/score/src/tlsallocsize.c
@@ -10,7 +10,7 @@
  */
 
 /*
- * Copyright (C) 2014, 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2014, 2022 embedded brains GmbH
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -58,29 +58,45 @@ uintptr_t _TLS_Get_allocation_size( void )
   allocation_size = _TLS_Allocation_size;
 
   if ( allocation_size == 0 ) {
-    uintptr_t alignment;
-
-    alignment = _TLS_Align_up( (uintptr_t) _TLS_Alignment );
-
-    allocation_size = size;
-    allocation_size += _TLS_Get_thread_control_block_area_size( alignment );
-#ifndef __i386__
-    allocation_size += sizeof( TLS_Dynamic_thread_vector );
-#endif
+    uintptr_t tls_align;
+    uintptr_t stack_align;
 
     /*
      * The TLS area is allocated in the thread storage area.  Each allocation
      * shall meet the stack alignment requirement.
      */
-    allocation_size = _TLS_Align_up( allocation_size );
+    stack_align = CPU_STACK_ALIGNMENT;
+    tls_align = RTEMS_ALIGN_UP( (uintptr_t) _TLS_Alignment, stack_align );
+
+#ifndef __i386__
+    /* Reserve space for the dynamic thread vector */
+    allocation_size +=
+      RTEMS_ALIGN_UP( sizeof( TLS_Dynamic_thread_vector ), stack_align );
+#endif
+
+    /* Reserve space for the thread control block */
+    allocation_size +=
+#if CPU_THREAD_LOCAL_STORAGE_VARIANT == 11
+      RTEMS_ALIGN_UP( sizeof( TLS_Thread_control_block ), tls_align );
+#else
+      RTEMS_ALIGN_UP( sizeof( TLS_Thread_control_block ), stack_align );
+#endif
+
+    /* Reserve space for the thread-local storage data */
+    allocation_size +=
+#if CPU_THREAD_LOCAL_STORAGE_VARIANT == 20
+      RTEMS_ALIGN_UP( size, tls_align );
+#else
+      RTEMS_ALIGN_UP( size, stack_align );
+#endif
 
     /*
      * The stack allocator does not support aligned allocations.  Allocate
      * enough to do the alignment manually.
      */
-    if ( alignment > CPU_STACK_ALIGNMENT ) {
-      _Assert( alignment % CPU_STACK_ALIGNMENT == 0 );
-      allocation_size += alignment - CPU_STACK_ALIGNMENT;
+    if ( tls_align > stack_align ) {
+      _Assert( tls_align % stack_align == 0 );
+      allocation_size += tls_align - stack_align;
     }
 
     if ( _Thread_Maximum_TLS_size != 0 ) {