diff options
author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-06-05 11:39:31 +0200 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-06-07 17:02:26 +0200 |
commit | dcb4daf8e18eaaf2dbf9acfa42b1e54643519cf2 (patch) | |
tree | 325ea3a216815d7598d455e1dc97302e58e87775 /cpukit/score/inline/rtems | |
parent | score: Simplify _Thread_Create_idle_helper() (diff) | |
download | rtems-dcb4daf8e18eaaf2dbf9acfa42b1e54643519cf2.tar.bz2 |
score: Simplify _CORE_semaphore_Seize_isr_disable
Diffstat (limited to 'cpukit/score/inline/rtems')
-rw-r--r-- | cpukit/score/inline/rtems/score/coresem.inl | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/cpukit/score/inline/rtems/score/coresem.inl b/cpukit/score/inline/rtems/score/coresem.inl index 69a7b2627d..aa021eb1db 100644 --- a/cpukit/score/inline/rtems/score/coresem.inl +++ b/cpukit/score/inline/rtems/score/coresem.inl @@ -70,7 +70,7 @@ RTEMS_INLINE_ROUTINE uint32_t _CORE_semaphore_Get_count( * @param[in] id is the Id of the owning API level Semaphore object * @param[in] wait is true if the thread is willing to wait * @param[in] timeout is the maximum number of ticks to block - * @param[in] level_p is a temporary variable used to contain the ISR + * @param[in] level is a temporary variable used to contain the ISR * disable level cookie * * @note There is currently no MACRO version of this routine. @@ -80,7 +80,7 @@ RTEMS_INLINE_ROUTINE void _CORE_semaphore_Seize_isr_disable( Objects_Id id, bool wait, Watchdog_Interval timeout, - ISR_Level *level_p + ISR_Level level ) { Thread_Control *executing; @@ -91,12 +91,12 @@ RTEMS_INLINE_ROUTINE void _CORE_semaphore_Seize_isr_disable( executing->Wait.return_code = CORE_SEMAPHORE_STATUS_SUCCESSFUL; if ( the_semaphore->count != 0 ) { the_semaphore->count -= 1; - _ISR_Enable( *level_p ); + _ISR_Enable( level ); return; } if ( !wait ) { - _ISR_Enable( *level_p ); + _ISR_Enable( level ); executing->Wait.return_code = CORE_SEMAPHORE_STATUS_UNSATISFIED_NOWAIT; return; } @@ -105,7 +105,7 @@ RTEMS_INLINE_ROUTINE void _CORE_semaphore_Seize_isr_disable( _Thread_queue_Enter_critical_section( &the_semaphore->Wait_queue ); executing->Wait.queue = &the_semaphore->Wait_queue; executing->Wait.id = id; - _ISR_Enable( *level_p ); + _ISR_Enable( level ); _Thread_queue_Enqueue( &the_semaphore->Wait_queue, timeout ); _Thread_Enable_dispatch(); |