summaryrefslogtreecommitdiffstats
path: root/cpukit/score/cpu
diff options
context:
space:
mode:
authorAlex Ivanov <alexivanov97@gmail.com>2012-11-30 15:34:17 -0600
committerJoel Sherrill <joel.sherrill@oarcorp.com>2012-11-30 15:35:36 -0600
commite0f91da505b5c907b545016645c07a3132696236 (patch)
treea3cbe53af4f52687425266b19082eb42ce34218b /cpukit/score/cpu
parent4a7dc83762e198263f5186695d2f7ffe41ec8cba (diff)
downloadrtems-e0f91da505b5c907b545016645c07a3132696236.tar.bz2
score misc: Score misc: Clean up Doxygen #9 (GCI 2012)
This patch is a task from GCI 2012 which improves the Doxygen comments in the RTEMS source. https://google-melange.appspot.com/gci/task/view/google/gci2012/7977211
Diffstat (limited to 'cpukit/score/cpu')
-rw-r--r--cpukit/score/cpu/h8300/cpu.c29
-rw-r--r--cpukit/score/cpu/lm32/cpu.c36
-rw-r--r--cpukit/score/cpu/lm32/irq.c16
-rw-r--r--cpukit/score/cpu/m32c/cpu.c19
-rw-r--r--cpukit/score/cpu/m32c/cpu_asm.c6
-rw-r--r--cpukit/score/cpu/mips/cpu.c46
-rw-r--r--cpukit/score/cpu/sparc/cpu.c50
-rw-r--r--cpukit/score/cpu/sparc64/cpu.c27
8 files changed, 50 insertions, 179 deletions
diff --git a/cpukit/score/cpu/h8300/cpu.c b/cpukit/score/cpu/h8300/cpu.c
index 558947b57f..3836e52304 100644
--- a/cpukit/score/cpu/h8300/cpu.c
+++ b/cpukit/score/cpu/h8300/cpu.c
@@ -1,6 +1,10 @@
-/*
- * Hitachi H8300 CPU Dependent Source
+/**
+ * @file
*
+ * @brief H8300 CPU Dependent Source
+ */
+
+/*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
@@ -37,12 +41,6 @@ void _CPU_Initialize(void)
/* FP context initialization support goes here */
}
-/*
- * _CPU_ISR_Get_level
- *
- * This routine returns the current interrupt level.
- */
-
uint32_t _CPU_ISR_Get_level( void )
{
unsigned int _ccr;
@@ -76,21 +74,6 @@ void _CPU_ISR_install_raw_handler(
H8BD_Install_IRQ(vector,new_handler,old_handler);
}
-/*
- * _CPU_ISR_install_vector
- *
- * This kernel routine installs the RTEMS handler for the
- * specified vector.
- *
- * Input parameters:
- * vector - interrupt vector number
- * old_handler - former ISR for this vector number
- * new_handler - replacement ISR for this vector number
- *
- * Output parameters: NONE
- *
- */
-
void _CPU_ISR_install_vector(
uint32_t vector,
proc_ptr new_handler,
diff --git a/cpukit/score/cpu/lm32/cpu.c b/cpukit/score/cpu/lm32/cpu.c
index d668dd4de6..6df5576e15 100644
--- a/cpukit/score/cpu/lm32/cpu.c
+++ b/cpukit/score/cpu/lm32/cpu.c
@@ -1,7 +1,10 @@
-/*
- * Lattice Mico32 (lm32) CPU Dependent Source
- *
+/**
+ * @file
*
+ * @brief LM32 CPU Dependent Source
+ */
+
+/*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
@@ -44,14 +47,6 @@ void _CPU_Initialize(void)
/* FP context initialization support goes here */
}
-/*
- * _CPU_ISR_Get_level
- *
- * LM32 Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-
uint32_t _CPU_ISR_Get_level( void )
{
/*
@@ -81,25 +76,6 @@ void _CPU_ISR_install_raw_handler(
*/
}
-/*
- * _CPU_ISR_install_vector
- *
- * This kernel routine installs the RTEMS handler for the
- * specified vector.
- *
- * Input parameters:
- * vector - interrupt vector number
- * old_handler - former ISR for this vector number
- * new_handler - replacement ISR for this vector number
- *
- * Output parameters: NONE
- *
- *
- * LM32 Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-
void _CPU_ISR_install_vector(
uint32_t vector,
proc_ptr new_handler,
diff --git a/cpukit/score/cpu/lm32/irq.c b/cpukit/score/cpu/lm32/irq.c
index a601ded807..37e9a28f53 100644
--- a/cpukit/score/cpu/lm32/irq.c
+++ b/cpukit/score/cpu/lm32/irq.c
@@ -1,8 +1,10 @@
-/*
- * lm32 interrupt handler
- *
- * Derived from c4x/irq.c and nios2/irq.c
+/**
+ * @file
*
+ * @brief LM32 Initialize the ISR Handler
+ */
+
+/*
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
@@ -21,12 +23,6 @@
#include <rtems/score/isr.h>
#include <rtems/score/percpu.h>
-/*
- * This routine provides the RTEMS interrupt management.
- *
- * Upon entry, interrupts are disabled
- */
-
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
unsigned long *_old_stack_ptr;
#endif
diff --git a/cpukit/score/cpu/m32c/cpu.c b/cpukit/score/cpu/m32c/cpu.c
index 4447cab916..afce6f03d4 100644
--- a/cpukit/score/cpu/m32c/cpu.c
+++ b/cpukit/score/cpu/m32c/cpu.c
@@ -1,6 +1,10 @@
-/*
- * XXX CPU Dependent Source
+/**
+ * @file
*
+ * @brief M32C CPU Dependent Source
+ */
+
+/*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
@@ -79,17 +83,6 @@ void _CPU_ISR_install_raw_handler(
/*
* _CPU_ISR_install_vector
*
- * This kernel routine installs the RTEMS handler for the
- * specified vector.
- *
- * Input parameters:
- * vector - interrupt vector number
- * old_handler - former ISR for this vector number
- * new_handler - replacement ISR for this vector number
- *
- * Output parameters: NONE
- *
- *
* NO_CPU Specific Information:
*
* XXX document implementation including references if appropriate
diff --git a/cpukit/score/cpu/m32c/cpu_asm.c b/cpukit/score/cpu/m32c/cpu_asm.c
index e6a40ee453..898390cbb2 100644
--- a/cpukit/score/cpu/m32c/cpu_asm.c
+++ b/cpukit/score/cpu/m32c/cpu_asm.c
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief M32C CPU Assembly File
+ */
+
/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s
*
* This file contains the basic algorithms for all assembly code used
diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c
index 657e53e071..5f7abeb368 100644
--- a/cpukit/score/cpu/mips/cpu.c
+++ b/cpukit/score/cpu/mips/cpu.c
@@ -1,7 +1,11 @@
/**
* @file
- *
- * Mips CPU Dependent Source
+ *
+ * @brief MIPS CPU Dependent Source
+ */
+
+/*
+ * MIPS CPU Dependent Source
*
* 2002: Greg Menke (gregory.menke@gsfc.nasa.gov)
* Overhauled interrupt level and interrupt enable/disable code
@@ -19,9 +23,7 @@
* wrote the JMR3904 BSP so this could be tested. Joel also
* added the new interrupt vectoring support in libcpu and
* tried to better support the various interrupt controllers.
- */
-
-/*
+ *
* Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
* COPYRIGHT (c) 1996 by Transition Networks Inc.
*
@@ -65,10 +67,6 @@ typedef uint64_t ESF_PTR_TYPE;
#endif
ESF_PTR_TYPE __exceptionStackFrame = 0;
-
-
-
-
/* _CPU_Initialize
*
* This routine performs processor dependent initialization.
@@ -93,12 +91,6 @@ void _CPU_Initialize(void)
#endif
}
-/*
- * _CPU_ISR_Get_level
- *
- * This routine returns the current interrupt level.
- */
-
uint32_t _CPU_ISR_Get_level( void )
{
unsigned int sr;
@@ -120,8 +112,6 @@ uint32_t _CPU_ISR_Get_level( void )
#endif
return sr;
}
-
-
void _CPU_ISR_Set_level( uint32_t new_level )
{
unsigned int sr, srbits;
@@ -172,31 +162,11 @@ void _CPU_ISR_Set_level( uint32_t new_level )
mips_set_sr( sr );
}
-/*
- * _CPU_Install_interrupt_stack
- */
-
void _CPU_Install_interrupt_stack( void )
{
/* we don't support this yet */
}
-/*
- * _CPU_Context_Initialize
- *
- * This kernel routine initializes the basic non-FP context area associated
- * with each thread.
- *
- * Input parameters:
- * the_context - pointer to the context area
- * stack_base - address of memory for the SPARC
- * size - size in bytes of the stack area
- * new_level - interrupt level for this context area
- * entry_point - the starting execution point for this this context
- * is_fp - TRUE if this context is associated with an FP thread
- *
- * Output parameters: NONE
- */
void _CPU_Context_Initialize(
Context_Control *the_context,
uintptr_t *stack_base,
@@ -222,8 +192,6 @@ void _CPU_Context_Initialize(
((intlvl & 1)?_INTON:0)) ) |
SR_CU0 | ((is_fp)?SR_CU1:0) | _EXTRABITS;
}
-
-
/*
* _CPU_Internal_threads_Idle_thread_body
*
diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c
index 78917261ea..baa15c0cbb 100644
--- a/cpukit/score/cpu/sparc/cpu.c
+++ b/cpukit/score/cpu/sparc/cpu.c
@@ -1,6 +1,10 @@
-/*
- * SPARC Dependent Source
+/**
+ * @file
*
+ * @brief SPARC CPU Dependent Source
+ */
+
+/*
* COPYRIGHT (c) 1989-2007.
* On-Line Applications Research Corporation (OAR).
*
@@ -70,15 +74,6 @@ void _CPU_Initialize(void)
_CPU_ISR_Dispatch_disable = 0;
}
-/*
- * _CPU_ISR_Get_level
- *
- * Input Parameters: NONE
- *
- * Output Parameters:
- * returns the current interrupt level (PIL field of the PSR)
- */
-
uint32_t _CPU_ISR_Get_level( void )
{
uint32_t level;
@@ -195,22 +190,6 @@ void _CPU_ISR_install_raw_handler(
}
-/*
- * _CPU_ISR_install_vector
- *
- * This kernel routine installs the RTEMS handler for the
- * specified vector.
- *
- * Input parameters:
- * vector - interrupt vector number
- * new_handler - replacement ISR for this vector number
- * old_handler - pointer to former ISR for this vector number
- *
- * Output parameters:
- * *old_handler - former ISR for this vector number
- *
- */
-
void _CPU_ISR_install_vector(
uint32_t vector,
proc_ptr new_handler,
@@ -247,23 +226,6 @@ void _CPU_ISR_install_vector(
_ISR_Vector_table[ real_vector ] = new_handler;
}
-/*
- * _CPU_Context_Initialize
- *
- * This kernel routine initializes the basic non-FP context area associated
- * with each thread.
- *
- * Input parameters:
- * the_context - pointer to the context area
- * stack_base - address of memory for the SPARC
- * size - size in bytes of the stack area
- * new_level - interrupt level for this context area
- * entry_point - the starting execution point for this this context
- * is_fp - TRUE if this context is associated with an FP thread
- *
- * Output parameters: NONE
- */
-
void _CPU_Context_Initialize(
Context_Control *the_context,
uint32_t *stack_base,
diff --git a/cpukit/score/cpu/sparc64/cpu.c b/cpukit/score/cpu/sparc64/cpu.c
index ac35dc413b..94f9340614 100644
--- a/cpukit/score/cpu/sparc64/cpu.c
+++ b/cpukit/score/cpu/sparc64/cpu.c
@@ -1,10 +1,14 @@
-/*
- * SPARC-v9 Dependent Source
+/**
+ * @file
*
+ * @brief SPARC64 CPU Dependent Source
+ */
+
+/*
* COPYRIGHT (c) 1989-2007.
* On-Line Applications Research Corporation (OAR).
*
- * This file is based on the SPARC cpu.c file. Modifications are made to
+ * This file is based on the SPARC cpu.c file. Modifications are made to
* provide support for the SPARC-v9.
* COPYRIGHT (c) 2010. Gedare Bloom.
*
@@ -55,23 +59,6 @@ void _CPU_Initialize(void)
_CPU_ISR_Dispatch_disable = 0;
}
-/*
- * _CPU_Context_Initialize
- *
- * This kernel routine initializes the basic non-FP context area associated
- * with each thread.
- *
- * Input parameters:
- * the_context - pointer to the context area
- * stack_base - address of memory for the SPARC
- * size - size in bytes of the stack area
- * new_level - interrupt level for this context area
- * entry_point - the starting execution point for this this context
- * is_fp - TRUE if this context is associated with an FP thread
- *
- * Output parameters: NONE
- */
-
void _CPU_Context_Initialize(
Context_Control *the_context,
void *stack_base,