diff options
| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2022-02-18 10:05:25 -0600 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-02-23 08:35:45 -0600 |
| commit | dbdf38ea7b2160fe1237a6cc5d3b23dea522c8ca (patch) | |
| tree | 409219b24ab34af35a22730a152b8317ac64e21c /cpukit/score/cpu | |
| parent | cpukit/libdebugger: Add pure swbreak capability (diff) | |
| download | rtems-dbdf38ea7b2160fe1237a6cc5d3b23dea522c8ca.tar.bz2 | |
microblaze: Decouple exceptions from interrupts
Exception handling should be enabled at all times during execution to
ensure that exceptions are not ignored which would cause further
problems. This separates use of the exception enable bit from use of the
interrupt enable bit in the machine status register so that they can be
manipulated independently.
Diffstat (limited to 'cpukit/score/cpu')
| -rw-r--r-- | cpukit/score/cpu/microblaze/cpu.c | 6 | ||||
| -rw-r--r-- | cpukit/score/cpu/microblaze/include/rtems/score/cpu.h | 10 |
2 files changed, 8 insertions, 8 deletions
diff --git a/cpukit/score/cpu/microblaze/cpu.c b/cpukit/score/cpu/microblaze/cpu.c index fe55ef5546..1e829a4714 100644 --- a/cpukit/score/cpu/microblaze/cpu.c +++ b/cpukit/score/cpu/microblaze/cpu.c @@ -142,9 +142,9 @@ void _CPU_ISR_Set_level( uint32_t level ) _CPU_MSR_GET( microblaze_switch_reg ); if ( level == 0 ) { - microblaze_switch_reg |= (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); + microblaze_switch_reg |= MICROBLAZE_MSR_IE; } else { - microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); + microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE); } _CPU_MSR_SET( microblaze_switch_reg ); @@ -158,7 +158,7 @@ uint32_t _CPU_ISR_Get_level( void ) /* This is unique. The MSR register contains an interrupt enable flag where * most other architectures have an interrupt disable flag. */ - return ( level & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE) ) == 0; + return ( level & MICROBLAZE_MSR_IE ) == 0; } void _CPU_ISR_install_vector( diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h index 5ca0609e91..181d247c5f 100644 --- a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h @@ -212,7 +212,7 @@ typedef struct { { \ unsigned int _new_msr; \ _CPU_MSR_GET(_isr_cookie); \ - _new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \ + _new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE); \ _CPU_MSR_SET(_new_msr); \ } @@ -221,9 +221,9 @@ typedef struct { uint32_t _microblaze_interrupt_enable; \ uint32_t _microblaze_switch_reg; \ \ - _microblaze_interrupt_enable = (_isr_cookie) & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \ + _microblaze_interrupt_enable = (_isr_cookie) & (MICROBLAZE_MSR_IE); \ _CPU_MSR_GET(_microblaze_switch_reg); \ - _microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \ + _microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE); \ _microblaze_switch_reg |= _microblaze_interrupt_enable; \ _CPU_MSR_SET(_microblaze_switch_reg); \ } @@ -232,7 +232,7 @@ typedef struct { { \ unsigned int _new_msr; \ _CPU_MSR_SET(_isr_cookie); \ - _new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \ + _new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE); \ _CPU_MSR_SET(_new_msr); \ } @@ -242,7 +242,7 @@ uint32_t _CPU_ISR_Get_level( void ); RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) { - return ( level & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE) ) != 0; + return ( level & MICROBLAZE_MSR_IE ) != 0; } void _CPU_Context_Initialize( |