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authorJoel Sherrill <joel.sherrill@OARcorp.com>1999-10-27 17:25:53 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>1999-10-27 17:25:53 +0000
commitae7325bdc85e1dd39f039b66ba20ca681712dcc3 (patch)
treeb90f303df4b2cefcd3155f164e16d177bcfb18f9 /cpukit/score/cpu
parent2ea8df3beb9c4e6bf76f1b261fdc3968c63f515b (diff)
downloadrtems-ae7325bdc85e1dd39f039b66ba20ca681712dcc3.tar.bz2
rxgen960 now compiles -- may not link.
Diffstat (limited to 'cpukit/score/cpu')
-rw-r--r--cpukit/score/cpu/i960/cpu.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/cpukit/score/cpu/i960/cpu.c b/cpukit/score/cpu/i960/cpu.c
index 07ca05f69b..b1f29ff1bf 100644
--- a/cpukit/score/cpu/i960/cpu.c
+++ b/cpukit/score/cpu/i960/cpu.c
@@ -67,10 +67,10 @@ unsigned32 _CPU_ISR_Get_level( void )
*/
#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
-#define _Is_vector_caching_enabled( _prcb ) \
+#define i960_vector_caching_enabled( _prcb ) \
((_prcb)->control_tbl->icon & 0x2000)
#elif defined(__i960RP__)
-#define _Is_vector_caching_enabled( _prcb ) \
+#define i960_vector_caching_enabled( _prcb ) \
((*((unsigned int *) ICON_ADDR)) & 0x2000)
#endif
@@ -93,7 +93,7 @@ void _CPU_ISR_install_raw_handler(
prcb->intr_tbl[ vector + 1 ] = new_handler;
- if ( _Is_vector_caching_enabled( prcb ) )
+ if ( i960_vector_caching_enabled( prcb ) )
if ( (vector & 0xf) == 0x2 ) /* cacheable? */
cached_intr_tbl[ vector >> 4 ] = new_handler;
}