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authorJoel Sherrill <joel.sherrill@OARcorp.com>2010-04-25 21:37:46 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2010-04-25 21:37:46 +0000
commita0cb87cbfc272d12265c3bb70417d9f1036bd59f (patch)
treeb5ca29e62536f5e3bca34cf69f671c07c7472fcb /cpukit/score/cpu
parent2010-04-25 Joel Sherrill <joel.sherrilL@OARcorp.com> (diff)
downloadrtems-a0cb87cbfc272d12265c3bb70417d9f1036bd59f.tar.bz2
2010-04-25 Joel Sherrill <joel.sherrilL@OARcorp.com>
* cpu.c, rtems/score/cpu.h: Move _CPU_Context_Initialize() to cpu.c so it is easier to make warning free.
Diffstat (limited to 'cpukit/score/cpu')
-rw-r--r--cpukit/score/cpu/mips/ChangeLog5
-rw-r--r--cpukit/score/cpu/mips/cpu.c43
-rw-r--r--cpukit/score/cpu/mips/rtems/score/cpu.h23
3 files changed, 57 insertions, 14 deletions
diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog
index bcb3c7cdba..d65aead2d4 100644
--- a/cpukit/score/cpu/mips/ChangeLog
+++ b/cpukit/score/cpu/mips/ChangeLog
@@ -1,5 +1,10 @@
2010-04-25 Joel Sherrill <joel.sherrilL@OARcorp.com>
+ * cpu.c, rtems/score/cpu.h: Move _CPU_Context_Initialize() to cpu.c so
+ it is easier to make warning free.
+
+2010-04-25 Joel Sherrill <joel.sherrilL@OARcorp.com>
+
* rtems/score/cpu.h: Remove warning in _CPU_Context_Initialize.
2010-03-27 Joel Sherrill <joel.sherrill@oarcorp.com>
diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c
index 04cad4dd1a..773f5f1334 100644
--- a/cpukit/score/cpu/mips/cpu.c
+++ b/cpukit/score/cpu/mips/cpu.c
@@ -251,6 +251,49 @@ void _CPU_Install_interrupt_stack( void )
/* we don't support this yet */
}
+/*
+ * _CPU_Context_Initialize
+ *
+ * This kernel routine initializes the basic non-FP context area associated
+ * with each thread.
+ *
+ * Input parameters:
+ * the_context - pointer to the context area
+ * stack_base - address of memory for the SPARC
+ * size - size in bytes of the stack area
+ * new_level - interrupt level for this context area
+ * entry_point - the starting execution point for this this context
+ * is_fp - TRUE if this context is associated with an FP thread
+ *
+ * Output parameters: NONE
+ */
+void _CPU_Context_Initialize(
+ Context_Control *the_context,
+ uintptr_t *stack_base,
+ uint32_t size,
+ uint32_t new_level,
+ void *entry_point,
+ bool is_fp
+)
+{
+ uintptr_t stack_tmp;
+ __MIPS_REGISTER_TYPE intlvl = new_level & 0xff;
+
+ stack_tmp = (uintptr_t)stack_base;
+ stack_tmp += ((size) - CPU_STACK_ALIGNMENT);
+ stack_tmp &= (__MIPS_REGISTER_TYPE) ~(CPU_STACK_ALIGNMENT - 1);
+
+ the_context->sp = (__MIPS_REGISTER_TYPE) stack_tmp;
+ the_context->fp = (__MIPS_REGISTER_TYPE) stack_tmp;
+ the_context->ra = (__MIPS_REGISTER_TYPE) (uintptr_t)entry_point;
+ the_context->c0_sr =
+ ((intlvl==0)? (mips_interrupt_mask() | 0x300 | _INTON):
+ ( ((intlvl<<9) & mips_interrupt_mask()) | 0x300 |
+ ((intlvl & 1)?_INTON:0)) ) |
+ SR_CU0 | ((is_fp)?SR_CU1:0) | _EXTRABITS;
+}
+
+
/*PAGE
*
* _CPU_Internal_threads_Idle_thread_body
diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h
index b4bdf7424d..096df3dcd0 100644
--- a/cpukit/score/cpu/mips/rtems/score/cpu.h
+++ b/cpukit/score/cpu/mips/rtems/score/cpu.h
@@ -416,7 +416,7 @@ typedef struct {
} Context_Control;
#define _CPU_Context_Get_SP( _context ) \
- (_context)->sp
+ (uintptr_t) (_context)->sp
/* WARNING: If this structure is modified, the constants in cpu.h
* must also be updated.
@@ -851,20 +851,15 @@ void _CPU_ISR_Set_level( uint32_t ); /* in cpu.c */
#define _EXTRABITS 0 /* make sure we're in user mode on MIPS1 processors */
#endif /* __mips == 1 */
-#define _CPU_Context_Initialize( _the_context, _stack_base, _size, _isr, _entry_point, _is_fp ) \
- { \
- uintptr_t _stack_tmp = \
- (uintptr_t)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
- uintptr_t _intlvl = _isr & 0xff; \
- _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
- (_the_context)->sp = (__MIPS_REGISTER_TYPE) _stack_tmp; \
- (_the_context)->fp = (__MIPS_REGISTER_TYPE) _stack_tmp; \
- (_the_context)->ra = (__MIPS_REGISTER_TYPE)_entry_point; \
- (_the_context)->c0_sr = ((_intlvl==0)?(mips_interrupt_mask() | 0x300 | _INTON): \
- ( ((_intlvl<<9) & mips_interrupt_mask()) | 0x300 | ((_intlvl & 1)?_INTON:0)) ) | \
- SR_CU0 | ((_is_fp)?SR_CU1:0) | _EXTRABITS; \
- }
+void _CPU_Context_Initialize(
+ Context_Control *the_context,
+ uintptr_t *stack_base,
+ uint32_t size,
+ uint32_t new_level,
+ void *entry_point,
+ bool is_fp
+);
/*