2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>

	PR 1573/cpukit
	* cpu_asm.S, rtems/score/cpu.h: Add a per cpu data structure which
	contains the information required by RTEMS for each CPU core. This
	encapsulates information such as thread executing, heir, idle and
	dispatch needed.

15 files changed, 94 insertions, 179 deletions

diff --git a/cpukit/score/cpu/avr/ChangeLog b/cpukit/score/cpu/avr/ChangeLog
index 772c4902bc..0bc3987dbd 100644
--- a/cpukit/score/cpu/avr/ChangeLog
+++ b/cpukit/score/cpu/avr/ChangeLog
@@ -1,3 +1,11 @@
+2010-06-28	Joel Sherrill <joel.sherrill@oarcorp.com>
+
+	PR 1573/cpukit
+	* cpu_asm.S, rtems/score/cpu.h: Add a per cpu data structure which
+	contains the information required by RTEMS for each CPU core. This
+	encapsulates information such as thread executing, heir, idle and
+	dispatch needed.
+
 2010-05-10	Joel Sherrill <joel.sherrilL@OARcorp.com>
 
 	* Makefile.am, cpu_asm.S, avr/boot.h, avr/common.h, avr/crc16.h,
diff --git a/cpukit/score/cpu/avr/cpu_asm.S b/cpukit/score/cpu/avr/cpu_asm.S
index dcff8856df..688e2e76c4 100644
--- a/cpukit/score/cpu/avr/cpu_asm.S
+++ b/cpukit/score/cpu/avr/cpu_asm.S
@@ -28,6 +28,7 @@
 
 #include <rtems/asm.h>
 #include <avr/sfr_defs.h>
+#include <rtems/score/percpu.h>
 
 
 #define jmpb_hi 	r25
@@ -438,11 +439,9 @@ void _ISR_Handler(void)
    *    goto the label "exit interrupt (simple case)"
    *
    *  if ( _Thread_Dispatch_disable_level )
-   *    _ISR_Signals_to_thread_executing = FALSE;
    *    goto the label "exit interrupt (simple case)"
    *
-   *  if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
-   *    _ISR_Signals_to_thread_executing = FALSE;
+   *  if ( _Context_Switch_necessary ) {
    *    call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
    *    prepare to get out of interrupt
    *    return from interrupt  (maybe to _ISR_Dispatch)
diff --git a/cpukit/score/cpu/avr/rtems/score/cpu.h b/cpukit/score/cpu/avr/rtems/score/cpu.h
index ab26ad9d1e..3b9281ff3c 100644
--- a/cpukit/score/cpu/avr/rtems/score/cpu.h
+++ b/cpukit/score/cpu/avr/rtems/score/cpu.h
@@ -456,26 +456,6 @@ typedef struct {
 SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
 
 /*
- *  On some CPUs, RTEMS supports a software managed interrupt stack.
- *  This stack is allocated by the Interrupt Manager and the switch
- *  is performed in _ISR_Handler.  These variables contain pointers
- *  to the lowest and highest addresses in the chunk of memory allocated
- *  for the interrupt stack.  Since it is unknown whether the stack
- *  grows up or down (in general), this give the CPU dependent
- *  code the option of picking the version it wants to use.
- *
- *  NOTE: These two variables are required if the macro
- *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
- *
- *  AVR Specific Information:
- *
- *  XXX document implementation including references if appropriate
- */
-
-SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
-SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
-
-/*
  *  Nothing prevents the porter from declaring more CPU specific variables.
  *
  *  AVR Specific Information:
diff --git a/cpukit/score/cpu/bfin/ChangeLog b/cpukit/score/cpu/bfin/ChangeLog
index 9bd39e15bc..2cfff848bd 100644
--- a/cpukit/score/cpu/bfin/ChangeLog
+++ b/cpukit/score/cpu/bfin/ChangeLog
@@ -1,3 +1,11 @@
+2010-06-28	Joel Sherrill <joel.sherrill@oarcorp.com>
+
+	PR 1573/cpukit
+	* cpu_asm.S, rtems/score/cpu.h: Add a per cpu data structure which
+	contains the information required by RTEMS for each CPU core. This
+	encapsulates information such as thread executing, heir, idle and
+	dispatch needed.
+
 2010-06-16	Joel Sherrill <joel.sherrilL@OARcorp.com>
 
 	* cpu_asm.S: Use SYM macro to be consistent with other ports.
diff --git a/cpukit/score/cpu/bfin/cpu_asm.S b/cpukit/score/cpu/bfin/cpu_asm.S
index 10d917ade7..7944550a3c 100644
--- a/cpukit/score/cpu/bfin/cpu_asm.S
+++ b/cpukit/score/cpu/bfin/cpu_asm.S
@@ -28,6 +28,7 @@
 #include <rtems/score/cpu_asm.h>
 #include <rtems/score/bfin.h>
 #include <rtems/bfin/bfin.h>
+#include <rtems/score/percpu.h>
 
 #define LO(con32) ((con32) & 0xFFFF)
 #define HI(con32) (((con32) >> 16) & 0xFFFF)
@@ -313,12 +314,8 @@ SYM(_CPU_Context_restore):
 
 
 	.globl SYM(_ISR_Handler)
-	.extern SYM(_CPU_Interrupt_stack_high)
-	.extern SYM(_ISR_Nest_level)
-	.extern SYM(_Thread_Dispatch_disable_level)
-	.extern SYM(_Context_Switch_necessary)
-	.extern SYM(_ISR_Signals_to_thread_executing)
 SYM(_ISR_Handler):
+	.extern SYM(_Thread_Dispatch_disable_level)
 	/* all interrupts are disabled at this point */
 	/* the following few items are pushed onto the task stack for at
 	   most one interrupt; nested interrupts will be using the interrupt
@@ -328,8 +325,8 @@ SYM(_ISR_Handler):
 	[--sp] = p0;
 	[--sp] = r1;
 	[--sp] = r0;
-	p0.h = SYM(_ISR_Nest_level);
-	p0.l = SYM(_ISR_Nest_level);
+	p0.h = ISR_NEST_LEVEL;
+	p0.l = ISR_NEST_LEVEL;
 	r0 = [p0];
 	r0 += 1;
 	[p0] = r0;
@@ -337,8 +334,8 @@ SYM(_ISR_Handler):
 	if !cc jump noStackSwitch;
 	/* setup interrupt stack */
 	r0 = sp;
-	p0.h = SYM(_CPU_Interrupt_stack_high);
-	p0.l = SYM(_CPU_Interrupt_stack_high);
+	p0.h = INTERRUPT_STACK_HIGH;
+	p0.l = INTERRUPT_STACK_HIGH;
 	sp = [p0];
 	[--sp] = r0;
 noStackSwitch:
@@ -452,8 +449,8 @@ noHandler:
 	/* this disables interrupts again */
 	reti = [sp++];
 
-	p0.h = SYM(_ISR_Nest_level);
-	p0.l = SYM(_ISR_Nest_level);
+	p0.h = ISR_NEST_LEVEL;
+	p0.l = ISR_NEST_LEVEL;
 	r0 = [p0];
 	r0 += -1;
 	[p0] = r0;
@@ -473,13 +470,8 @@ noStackRestore:
 	if !cc jump noDispatch
 
 	/* do thread dispatch if necessary */
-	p0.h = SYM(_Context_Switch_necessary);
-	p0.l = SYM(_Context_Switch_necessary);
-	r0 = B[p0] (Z);
-	cc = r0 == 0;
-	p0.h = SYM(_ISR_Signals_to_thread_executing);
-	p0.l = SYM(_ISR_Signals_to_thread_executing);
-	if !cc jump doDispatch
+	p0.h = DISPATCH_NEEDED;
+	p0.l = DISPATCH_NEEDED;
 	r0 = B[p0] (Z);
 	cc = r0 == 0;
 	if cc jump noDispatch
diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h b/cpukit/score/cpu/bfin/rtems/score/cpu.h
index f64b8e50ce..c688eb2686 100644
--- a/cpukit/score/cpu/bfin/rtems/score/cpu.h
+++ b/cpukit/score/cpu/bfin/rtems/score/cpu.h
@@ -544,20 +544,6 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
  *  XXX document implementation including references if appropriate
  */
 
-/**
- *  @ingroup CPUInterrupt
- *  This variable points to the lowest physical address of the interrupt
- *  stack.
- */
-SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
-
-/**
- *  @ingroup CPUInterrupt
- *  This variable points to the lowest physical address of the interrupt
- *  stack.
- */
-SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
-
 /*
  *  Nothing prevents the porter from declaring more CPU specific variables.
  *
diff --git a/cpukit/score/cpu/m68k/ChangeLog b/cpukit/score/cpu/m68k/ChangeLog
index f424d59e50..0f89015a63 100644
--- a/cpukit/score/cpu/m68k/ChangeLog
+++ b/cpukit/score/cpu/m68k/ChangeLog
@@ -1,3 +1,11 @@
+2010-06-28	Joel Sherrill <joel.sherrill@oarcorp.com>
+
+	PR 1573/cpukit
+	* cpu_asm.S, rtems/score/cpu.h: Add a per cpu data structure which
+	contains the information required by RTEMS for each CPU core. This
+	encapsulates information such as thread executing, heir, idle and
+	dispatch needed.
+
 2010-04-08	Till Straumann <strauman@slac.stanford.edu>
 
 	* cpu_asm.S, rtems/score/cpu.h: On uC5282, the thread restart needed to
diff --git a/cpukit/score/cpu/m68k/cpu_asm.S b/cpukit/score/cpu/m68k/cpu_asm.S
index a8bbdef2ea..afc6ad2878 100644
--- a/cpukit/score/cpu/m68k/cpu_asm.S
+++ b/cpukit/score/cpu/m68k/cpu_asm.S
@@ -19,6 +19,7 @@
 #endif
 
 #include <rtems/asm.h>
+#include <rtems/score/percpu.h>
 
 /*  void _CPU_Context_switch( run_context, heir_context )
  *
@@ -263,8 +264,8 @@ SYM (_ISR_Handler):
 
 #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
         | Make a0 point just above interrupt stack
-        movel   _CPU_Interrupt_stack_high,a0
-        cmpl    _CPU_Interrupt_stack_low,a7  | stack below interrupt stack?
+        movel   INTERRUPT_STACK_HIGH,a0
+        cmpl    INTERRUPT_STACK_LOW,a7  | stack below interrupt stack?
         bcs.b   1f                      | yes, switch to interrupt stack
         cmpl    a0,a7                   | stack above interrupt stack?
         bcs.b   2f                      | no, do not switch stacks
@@ -276,7 +277,7 @@ SYM (_ISR_Handler):
 2:
 #endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
 
-        addql   #1,SYM(_ISR_Nest_level) | one nest level deeper
+        addql   #1,ISR_NEST_LEVEL        | one nest level deeper
 
         movel   SYM (_ISR_Vector_table),a0 | a0= base of RTEMS table
 #if ( M68K_HAS_PREINDEXING == 1 )
@@ -290,10 +291,10 @@ SYM (_ISR_Handler):
         movel   d0,a7@-                  | push vector number
         jbsr    a0@                      | invoke the user ISR
         addql   #4,a7                    | remove vector number
-        subql   #1,SYM(_ISR_Nest_level)  | Reduce interrupt-nesting count
+        subql   #1,ISR_NEST_LEVEL        | Reduce interrupt-nesting count
 
 #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
-        movel   _CPU_Interrupt_stack_high,a0
+        movel   INTERRUPT_STACK_HIGH,a0
         subql   #4,a0
         cmpl    a0,a7                   | At top of interrupt stack?
         bne.b   1f                      | No, do not restore task stack pointer
@@ -322,16 +323,11 @@ SYM (_ISR_Handler):
         beq.b   exit
   #endif
 #endif
-        tstb    SYM (_Context_Switch_necessary)
+        tstb    DISPATCH_NEEDED
                                          | Is thread switch necessary?
-        bne.b   bframe                   | Yes, invoke dispatcher
-
-        tstb    SYM (_ISR_Signals_to_thread_executing)
-                                         | signals sent to Run_thread
-                                         |   while in interrupt handler?
         beq.b   exit                     | No, then exit
 
-bframe: clrb    SYM (_ISR_Signals_to_thread_executing)
+bframe: 
                                          | If sent, will be processed
 #if ( M68K_HAS_SEPARATE_STACKS == 1 )
         movec   msp,a0                   | a0 = master stack pointer
diff --git a/cpukit/score/cpu/m68k/rtems/score/cpu.h b/cpukit/score/cpu/m68k/rtems/score/cpu.h
index 461f3dbc28..b4e1780bc6 100644
--- a/cpukit/score/cpu/m68k/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m68k/rtems/score/cpu.h
@@ -308,9 +308,6 @@ typedef struct {
 
 /* variables */
 
-SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
-SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
-
 extern void*                     _VBR;
 
 #if ( M68K_HAS_VBR == 0 )
diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog
index d262d33414..a6aae9c1d9 100644
--- a/cpukit/score/cpu/mips/ChangeLog
+++ b/cpukit/score/cpu/mips/ChangeLog
@@ -1,3 +1,11 @@
+2010-06-28	Joel Sherrill <joel.sherrill@oarcorp.com>
+
+	PR 1573/cpukit
+	* cpu_asm.S, rtems/score/cpu.h: Add a per cpu data structure which
+	contains the information required by RTEMS for each CPU core. This
+	encapsulates information such as thread executing, heir, idle and
+	dispatch needed.
+
 2010-06-16	Joel Sherrill <joel.sherrill@oarcorp.com>
 
 	* cpu_asm.S: Remove trailing tabs.
diff --git a/cpukit/score/cpu/mips/cpu_asm.S b/cpukit/score/cpu/mips/cpu_asm.S
index 63ec57cb84..fb6e118e83 100644
--- a/cpukit/score/cpu/mips/cpu_asm.S
+++ b/cpukit/score/cpu/mips/cpu_asm.S
@@ -57,6 +57,7 @@
 #include <rtems/asm.h>
 #include <rtems/mips/iregdef.h>
 #include <rtems/mips/idtcpu.h>
+#include <rtems/score/percpu.h>
 
 #define ASSEMBLY_ONLY
 #include <rtems/score/cpu.h>
@@ -201,8 +202,6 @@
 
 ASM_EXTERN(__exceptionStackFrame, SZ_INT)
 
-
-
 /*
  *  _CPU_Context_save_fp_context
  *
@@ -585,20 +584,12 @@ FRAME(_CPU_Context_restore,sp,0,ra)
 
 ENDFRAME(_CPU_Context_restore)
 
-
-ASM_EXTERN(_ISR_Nest_level,4)
 ASM_EXTERN(_Thread_Dispatch_disable_level,4)
-ASM_EXTERN(_Context_Switch_necessary,1)
-ASM_EXTERN(_ISR_Signals_to_thread_executing,1)
 ASM_EXTERN(_Thread_Executing,4)
 
 .extern _Thread_Dispatch
 .extern _ISR_Vector_table
 
-
-
-
-
 /*  void _DBG_Handler()
  *
  *  This routine services the (at least) MIPS1 debug vector,
@@ -606,10 +597,7 @@ ASM_EXTERN(_Thread_Executing,4)
  *  while optional, is best located here because its intrinsically
  *  associated with exceptions in general & thus tied pretty
  *  closely to _ISR_Handler.
- *
  */
-
-
 FRAME(_DBG_Handler,sp,0,ra)
         .set noreorder
 	la	k0,_ISR_Handler
@@ -618,10 +606,6 @@ FRAME(_DBG_Handler,sp,0,ra)
 	.set reorder
 ENDFRAME(_DBG_Handler)
 
-
-
-
-
 /*  void __ISR_Handler()
  *
  *  This routine provides the RTEMS interrupt management.
@@ -693,7 +677,7 @@ FRAME(_ISR_Handler,sp,0,ra)
 
 
 #ifdef INSTRUMENT_EXECUTING_THREAD
-	lw t2, _Thread_Executing
+	lw t2, THREAD_EXECUTING
 	NOP
 	sw t2, 0x8001FFF0
 #endif
@@ -904,10 +888,10 @@ _ISR_Handler_1:
   /*
    *  _ISR_Nest_level++;
    */
-        lw	t0,_ISR_Nest_level
+        lw	t0,ISR_NEST_LEVEL
 	NOP
         add	t0,t0,1
-        sw	t0,_ISR_Nest_level
+        sw	t0,ISR_NEST_LEVEL
   /*
    *  _Thread_Dispatch_disable_level++;
    */
@@ -940,10 +924,10 @@ _ISR_Handler_1:
   /*
    *  --_ISR_Nest_level;
    */
-        lw	t2,_ISR_Nest_level
+        lw	t2,ISR_NEST_LEVEL
 	NOP
         add	t2,t2,-1
-        sw	t2,_ISR_Nest_level
+        sw	t2,ISR_NEST_LEVEL
   /*
    *  --_Thread_Dispatch_disable_level;
    */
@@ -965,20 +949,19 @@ _ISR_Handler_1:
    *    restore stack
    *  #endif
    *
-   *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
+   *  if !_Context_Switch_necessary 
    *    goto the label "exit interrupt (simple case)"
    */
-        lbu	t0,_Context_Switch_necessary
-        lbu	t1,_ISR_Signals_to_thread_executing
+        lbu	t0,DISPATCH_NEEDED
 	NOP
-        or	t0,t0,t1
+        or	t0,t0,t0
         beq	t0,zero,_ISR_Handler_exit
         NOP
 
 
 
 #ifdef INSTRUMENT_EXECUTING_THREAD
-	lw	t0,_Thread_Executing
+	lw	t0,THREAD_EXECUTING
 	NOP
 	sw	t0,0x8001FFF4
 #endif
@@ -1068,7 +1051,7 @@ _ISR_Handler_1:
 
 
 #ifdef INSTRUMENT_EXECUTING_THREAD
-	lw	t0,_Thread_Executing
+	lw	t0,THREAD_EXECUTING
 	NOP
 	sw	t0,0x8001FFF8
 #endif
@@ -1093,7 +1076,7 @@ _ISR_Handler_exit:
 	/* restore context from stack */
 
 #ifdef INSTRUMENT_EXECUTING_THREAD
-	lw	t0,_Thread_Executing
+	lw	t0,THREAD_EXECUTING
 	NOP
 	sw	t0, 0x8001FFFC
 #endif
diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h
index 096df3dcd0..aab4d4893d 100644
--- a/cpukit/score/cpu/mips/rtems/score/cpu.h
+++ b/cpukit/score/cpu/mips/rtems/score/cpu.h
@@ -617,22 +617,6 @@ typedef struct
 SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
 
 /*
- *  On some CPUs, RTEMS supports a software managed interrupt stack.
- *  This stack is allocated by the Interrupt Manager and the switch
- *  is performed in _ISR_Handler.  These variables contain pointers
- *  to the lowest and highest addresses in the chunk of memory allocated
- *  for the interrupt stack.  Since it is unknown whether the stack
- *  grows up or down (in general), this give the CPU dependent
- *  code the option of picking the version it wants to use.
- *
- *  NOTE: These two variables are required if the macro
- *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
- */
-
-SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
-SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
-
-/*
  *  Nothing prevents the porter from declaring more CPU specific variables.
  */
 
diff --git a/cpukit/score/cpu/sparc/ChangeLog b/cpukit/score/cpu/sparc/ChangeLog
index 1951d40961..5016d21b03 100644
--- a/cpukit/score/cpu/sparc/ChangeLog
+++ b/cpukit/score/cpu/sparc/ChangeLog
@@ -1,3 +1,11 @@
+2010-06-28	Joel Sherrill <joel.sherrill@oarcorp.com>
+
+	PR 1573/cpukit
+	* cpu_asm.S, rtems/score/cpu.h: Add a per cpu data structure which
+	contains the information required by RTEMS for each CPU core. This
+	encapsulates information such as thread executing, heir, idle and
+	dispatch needed.
+
 2010-03-27	Joel Sherrill <joel.sherrill@oarcorp.com>
 
 	* cpu.c, cpu_asm.S: Add include of config.h
diff --git a/cpukit/score/cpu/sparc/cpu_asm.S b/cpukit/score/cpu/sparc/cpu_asm.S
index e5ecc4c084..363ce80ad9 100644
--- a/cpukit/score/cpu/sparc/cpu_asm.S
+++ b/cpukit/score/cpu/sparc/cpu_asm.S
@@ -4,7 +4,7 @@
  *  in an specific CPU port of RTEMS.  These algorithms must be implemented
  *  in assembly language.
  *
- *  COPYRIGHT (c) 1989-2007.
+ *  COPYRIGHT (c) 1989-2010.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -26,6 +26,7 @@
 #endif
 
 #include <rtems/asm.h>
+#include <rtems/system.h>
 
 #if (SPARC_HAS_FPU == 1)
 
@@ -471,7 +472,7 @@ save_isf:
          *  Register usage for this section:
          *
          *    l4 = _Thread_Dispatch_disable_level pointer
-         *    l5 = _ISR_Nest_level pointer
+         *    l5 = per cpu info pointer
          *    l6 = _Thread_Dispatch_disable_level value
          *    l7 = _ISR_Nest_level value
          *
@@ -481,14 +482,17 @@ save_isf:
 
         sethi    %hi(SYM(_Thread_Dispatch_disable_level)), %l4
         ld       [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6
-        sethi    %hi(SYM(_ISR_Nest_level)), %l5
-        ld       [%l5 + %lo(SYM(_ISR_Nest_level))], %l7
+
+        sethi    %hi(_Per_CPU_Information), %l5
+        add      %l5, %lo(_Per_CPU_Information), %l5
+
+	ld       [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
 
         add      %l6, 1, %l6
         st       %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))]
 
         add      %l7, 1, %l7
-        st       %l7, [%l5 + %lo(SYM(_ISR_Nest_level))]
+        st       %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
 
         /*
          *  If ISR nest level was zero (now 1), then switch stack.
@@ -498,8 +502,8 @@ save_isf:
         subcc    %l7, 1, %l7             ! outermost interrupt handler?
         bnz      dont_switch_stacks      ! No, then do not switch stacks
 
-        sethi    %hi(SYM(_CPU_Interrupt_stack_high)), %g4
-        ld       [%g4 + %lo(SYM(_CPU_Interrupt_stack_high))], %sp
+        nop
+	ld       [%l5 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
 
 dont_switch_stacks:
         /*
@@ -644,7 +648,7 @@ dont_fix_pil2:
         sub      %l6, 1, %l6
         st       %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))]
 
-        st       %l7, [%l5 + %lo(SYM(_ISR_Nest_level))]
+        st       %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
 
         /*
          *  If dispatching is disabled (includes nested interrupt case),
@@ -660,8 +664,7 @@ dont_fix_pil2:
         ld       [%l6 + %lo(SYM(_CPU_ISR_Dispatch_disable))], %l7
         orcc     %l7, %g0, %g0   ! Is this thread already doing an ISR?
         bnz      simple_return   ! Yes, then do a "simple" exit
-        ! NOTE: Use the delay slot
-        sethi    %hi(SYM(_Context_Switch_necessary)), %l4
+        nop
 
 
         /*
@@ -669,27 +672,11 @@ dont_fix_pil2:
          *  return to the interrupt dispatcher.
          */
 
-        ldub     [%l4 + %lo(SYM(_Context_Switch_necessary))], %l5
+        ldub     [%l5 + PER_CPU_DISPATCH_NEEDED], %l5
 
         orcc     %l5, %g0, %g0   ! Is thread switch necessary?
-        bnz      SYM(_ISR_Dispatch) ! yes, then invoke the dispatcher
-        ! NOTE: Use the delay slot
-        sethi    %hi(SYM(_ISR_Signals_to_thread_executing)), %l6
-
-        /*
-         *  Finally, check to see if signals were sent to the currently
-         *  executing task.  If so, we need to invoke the interrupt dispatcher.
-         */
-
-        ldub     [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))], %l7
-
-        orcc     %l7, %g0, %g0   ! Were signals sent to the currently
-                                 !   executing thread?
-        bz       simple_return   ! yes, then invoke the dispatcher
-                                 ! use the delay slot to clear the signals
-                                 !   to the currently executing task flag
-        st       %g0, [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))]
-
+        bz       simple_return   ! no, then do a simple return
+        nop
 
         /*
          *  Invoke interrupt dispatcher.
@@ -737,28 +724,14 @@ isr_dispatch:
          *  _Thread_Dispatch before leaving this ISR Dispatch context.
          */
 
-        sethi    %hi(SYM(_Context_Switch_necessary)), %l4
-        ldub     [%l4 + %lo(SYM(_Context_Switch_necessary))], %l5
-
-        ! NOTE: Use some of delay slot to start loading this
-        sethi    %hi(SYM(_ISR_Signals_to_thread_executing)), %l6
-        ldub     [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))], %l7
+        sethi    %hi(_Per_CPU_Information), %l5
+        add      %l5, %lo(_Per_CPU_Information), %l5
 
-        orcc     %l5, %g0, %g0   ! Is thread switch necessary?
-        bnz      dispatchAgain   ! yes, then invoke the dispatcher AGAIN
-        ! NOTE: Use the delay slot to catch the orcc below
+        ldub     [%l5 + PER_CPU_DISPATCH_NEEDED], %l7
 
-        /*
-         *  Finally, check to see if signals were sent to the currently
-         *  executing task.  If so, we need to invoke the interrupt dispatcher.
-         */
-
-        ! NOTE: Delay slots above were used to perform the load AND
-        !       this orcc falls into the delay slot for bnz above
-        orcc     %l7, %g0, %g0   ! Were signals sent to the currently
-                                 !   executing thread?
+        orcc     %l7, %g0, %g0    ! Is thread switch necesary?
         bz       allow_nest_again ! No, then clear out and return
-        ! NOTE: use the delay slot from the bz to load 3 into %g1
+        nop
 
         ! Yes, then invoke the dispatcher
 dispatchAgain:
diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h
index 3e30e9a7f8..2b2b0f5b32 100644
--- a/cpukit/score/cpu/sparc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h
@@ -523,22 +523,6 @@ typedef struct {
 SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT;
 
 /*
- *  This stack is allocated by the Interrupt Manager and the switch
- *  is performed in _ISR_Handler.  These variables contain pointers
- *  to the lowest and highest addresses in the chunk of memory allocated
- *  for the interrupt stack.  Since it is unknown whether the stack
- *  grows up or down (in general), this give the CPU dependent
- *  code the option of picking the version it wants to use.  Thus
- *  both must be present if either is.
- *
- *  The SPARC supports a software based interrupt stack and these
- *  are required.
- */
-
-SCORE_EXTERN void *_CPU_Interrupt_stack_low;
-SCORE_EXTERN void *_CPU_Interrupt_stack_high;
-
-/*
  *  This flag is context switched with each thread.  It indicates
  *  that THIS thread has an _ISR_Dispatch stack frame on its stack.
  *  By using this flag, we can avoid nesting more interrupt dispatching
@@ -965,6 +949,7 @@ void _CPU_Context_restore_fp(
   Context_Control_fp **fp_context_ptr
 );
 
+
 /*
  *  CPU_swap_u32
  *