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authorKinsey Moore <kinsey.moore@oarcorp.com>2022-01-03 16:45:26 -0600
committerJoel Sherrill <joel@rtems.org>2022-03-12 11:55:11 -0600
commit3e3393ac1e5b25d4b172dd1e9b77d202753739f7 (patch)
tree3717f3394a93ba52a6a518e53f3fd5de7b90f3c2 /cpukit/score/cpu
parentarm: Fix PMSA section to region mapping (diff)
downloadrtems-3e3393ac1e5b25d4b172dd1e9b77d202753739f7.tar.bz2
cpukit/aarch64: Add Per_CPU_Control accessor
Add an architecture-specific implementation for _CPU_Get_current_per_CPU_control() to reduce overhead for getting the current CPU's Per_CPU_Control structure.
Diffstat (limited to 'cpukit/score/cpu')
-rw-r--r--cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
index 90fd48ad4e..ffdef2f30a 100644
--- a/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
@@ -125,6 +125,29 @@ typedef struct {
uint64_t register_fpcr;
} CPU_Interrupt_frame;
+#ifdef RTEMS_SMP
+
+static inline
+struct Per_CPU_Control *_AARCH64_Get_current_per_CPU_control( void )
+{
+ struct Per_CPU_Control *cpu_self;
+ uint64_t value;
+
+ __asm__ volatile (
+ "mrs %0, TPIDR_EL1" : "=&r" ( value ) : : "memory"
+ );
+
+ /* Use EL1 Thread ID Register (TPIDR_EL1) */
+ cpu_self = (struct Per_CPU_Control *)(uintptr_t)value;
+
+ return cpu_self;
+}
+
+#define _CPU_Get_current_per_CPU_control() \
+ _AARCH64_Get_current_per_CPU_control()
+
+#endif /* RTEMS_SMP */
+
void _CPU_Context_volatile_clobber( uintptr_t pattern );
void _CPU_Context_validate( uintptr_t pattern );