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authorKinsey Moore <kinsey.moore@oarcorp.com>2022-01-26 10:57:49 -0600
committerJoel Sherrill <joel@rtems.org>2022-02-23 08:35:45 -0600
commit3317d1e8f0be3b14d94d356ad8437db07c5cd7cb (patch)
tree6fc50eda803d188f625610210c10261723cff729 /cpukit/score/cpu
parentcpukit/libdebugger: Avoid cascade for interrupts (diff)
downloadrtems-3317d1e8f0be3b14d94d356ad8437db07c5cd7cb.tar.bz2
cpukit/libdebugger: Add MicroBlaze support
Add MicroBlaze support for libdebugger. This uses only software break type instructions to provide self-hosted GDB debugging support for applications since internal control of debug hardware is not possible. Also of note, this implementation for MicroBlaze would typically use the brki instruction for software break, but instead uses an illegal opcode to manage software breaks as exceptions. This is due to poor interaction with the debug hardware where the debug hardware will intercept software breaks instead of allowing the software break vector to execute.
Diffstat (limited to 'cpukit/score/cpu')
-rw-r--r--cpukit/score/cpu/microblaze/include/rtems/score/cpu.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
index 181d247c5f..a486c3d2b3 100644
--- a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h
@@ -208,6 +208,30 @@ typedef struct {
#define _CPU_MSR_SET( _msr_value ) \
{ __asm__ volatile ("mts rmsr, %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
+#define MICROBLAZE_PVR0_VERSION_GET( _pvr0_value ) \
+ ( ( _pvr0_value >> 8 ) & 0xff )
+
+#define _CPU_PVR0_GET( _pvr0_value ) \
+ do { \
+ ( _pvr0_value ) = 0; \
+ __asm__ volatile ( "mfs %0, rpvr0" : "=&r" ( ( _pvr0_value ) ) ); \
+ } while ( 0 )
+
+#define MICROBLAZE_PVR3_BP_GET( _pvr3_value ) \
+ ( ( _pvr3_value >> 25 ) & 0xf )
+
+#define MICROBLAZE_PVR3_RWP_GET( _pvr3_value ) \
+ ( ( _pvr3_value >> 19 ) & 0x7 )
+
+#define MICROBLAZE_PVR3_WWP_GET( _pvr3_value ) \
+ ( ( _pvr3_value >> 13 ) & 0x7 )
+
+#define _CPU_PVR3_GET( _pvr3_value ) \
+ do { \
+ ( _pvr3_value ) = 0; \
+ __asm__ volatile ( "mfs %0, rpvr3" : "=&r" ( ( _pvr3_value ) ) ); \
+ } while ( 0 )
+
#define _CPU_ISR_Disable( _isr_cookie ) \
{ \
unsigned int _new_msr; \