diff options
| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2022-07-14 18:10:45 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-07-21 12:26:35 -0500 |
| commit | 10ef7087f62bb83b36e8d9fc98e89e8f81d33fb9 (patch) | |
| tree | 44c96108608c504b8c31b46da15394f9e1e55790 /cpukit/score/cpu | |
| parent | Support _REENT_THREAD_LOCAL Newlib configuration (diff) | |
| download | rtems-10ef7087f62bb83b36e8d9fc98e89e8f81d33fb9.tar.bz2 | |
aarch64: Use page table level 0
This alters the AArch64 page table generation and mapping code and MMU
configuration to use page table level 0 in addition to levels 1, 2, and
3. This allows the mapping of up to 48 bits of memory space and is the
maximum that can be mapped without relying on additional processor
extensions. Mappings are restricted based on the number of physical
address bits that the CPU supports.
Diffstat (limited to 'cpukit/score/cpu')
| -rw-r--r-- | cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h b/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h index 6b6296bb7a..0d65004f88 100644 --- a/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h +++ b/cpukit/score/cpu/aarch64/include/libcpu/mmu-vmsav8-64.h @@ -60,7 +60,6 @@ extern "C" { #define MMU_PAGE_BITS 12 #define MMU_PAGE_SIZE ( 1 << MMU_PAGE_BITS ) #define MMU_BITS_PER_LEVEL 9 -#define MMU_TOP_LEVEL_PAGE_BITS ( 2 * MMU_BITS_PER_LEVEL + MMU_PAGE_BITS ) #define AARCH64_MMU_FLAGS_BASE \ ( MMU_DESC_VALID | MMU_DESC_SH_INNER | MMU_DESC_AF ) |