2006-01-16 Joel Sherrill <joel@OARcorp.com>

	* rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
	As a side-effect, grammar and spelling errors were corrected, spacing
	errors were address, and some variable names were improved.

1 files changed, 10 insertions, 4 deletions

diff --git a/cpukit/score/cpu/unix/rtems/score/cpu.h b/cpukit/score/cpu/unix/rtems/score/cpu.h
index ff45eec8bc..f2058fc655 100644
--- a/cpukit/score/cpu/unix/rtems/score/cpu.h
+++ b/cpukit/score/cpu/unix/rtems/score/cpu.h
@@ -12,6 +12,13 @@
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
+ *  COPYRIGHT (c) 1989-2006.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
  *  $Id$
  */
 
@@ -121,8 +128,7 @@ extern "C" {
  *  If TRUE, then the memory is allocated during initialization.
  *  If FALSE, then the memory is allocated during initialization.
  *
- *  This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
- *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
+ *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
  */
 
 #define CPU_ALLOCATE_INTERRUPT_STACK FALSE
@@ -608,7 +614,7 @@ SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
 
 /*
- *  Should be large enough to run all RTEMS tests.  This insures
+ *  Should be large enough to run all RTEMS tests.  This ensures
  *  that a "reasonable" small application should not have any problems.
  */
 
@@ -1008,7 +1014,7 @@ void _CPU_Fatal_error(
  *  Some CPUs have special instructions which swap a 32-bit quantity in
  *  a single instruction (e.g. i486).  It is probably best to avoid
  *  an "endian swapping control bit" in the CPU.  One good reason is
- *  that interrupts would probably have to be disabled to insure that
+ *  that interrupts would probably have to be disabled to ensure that
  *  an interrupt does not try to access the same "chunk" with the wrong
  *  endian.  Another good reason is that on some CPUs, the endian bit
  *  endianness for ALL fetches -- both code and data -- so the code