sparc: Use Per_CPU_Control::isr_dispatch_disable

Update #2751.

1 files changed, 5 insertions, 16 deletions

diff --git a/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h
index 51071ab267..5563db8911 100644
--- a/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h
@@ -70,21 +70,15 @@
 #if ( SPARC_HAS_FPU == 1 )
   #define CPU_PER_CPU_CONTROL_SIZE 8
 #else
-  #define CPU_PER_CPU_CONTROL_SIZE 4
+  #define CPU_PER_CPU_CONTROL_SIZE 0
 #endif
 
-/**
- * @brief Offset of the CPU_Per_CPU_control::isr_dispatch_disable field
- * relative to the Per_CPU_Control begin.
- */
-#define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0
-
 #if ( SPARC_HAS_FPU == 1 )
   /**
    * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
    * Per_CPU_Control begin.
    */
-  #define SPARC_PER_CPU_FSR_OFFSET 4
+  #define SPARC_PER_CPU_FSR_OFFSET 0
 #endif
 
 #ifndef ASM
@@ -94,14 +88,6 @@ extern "C" {
 #endif
 
 typedef struct {
-  /**
-   * This flag is context switched with each thread.  It indicates
-   * that THIS thread has an _ISR_Dispatch stack frame on its stack.
-   * By using this flag, we can avoid nesting more interrupt dispatching
-   * attempts on a previously interrupted thread's stack.
-   */
-  uint32_t isr_dispatch_disable;
-
 #if ( SPARC_HAS_FPU == 1 )
   /**
    * @brief Memory location to store the FSR register during interrupt
@@ -111,6 +97,9 @@ typedef struct {
    * floating point operations in progress.
    */
   uint32_t fsr;
+
+  /* See Per_CPU_Control::Interrupt_frame */
+  uint32_t reserved_for_alignment_of_interrupt_frame;
 #endif
 } CPU_Per_CPU_control;