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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2021-06-21 11:24:27 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2021-06-24 11:36:28 +0200 |
commit | d73e657e063e3d34db16fa4bce6c2ab1e5e22ec4 (patch) | |
tree | 1794ed9c294e636b567d8ad2293df63576e6ca0e /cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h | |
parent | sparc: Move ISR handler install routines (diff) | |
download | rtems-d73e657e063e3d34db16fa4bce6c2ab1e5e22ec4.tar.bz2 |
sparc: More reliable bad trap handling
Statically initialize the trap table in start.S to jump to _SPARC_Bad_trap()
for all unexpected traps. This enables a proper RTEMS fatal error handling
right from the start. Do not rely on the stack and register settings which
caused an unexpected trap. Use the ISR stack of the processor to do the fatal
error handling. Save the full context which caused the trap. Fatal error
handler may use it for error logging.
Unify the _CPU_Exception_frame_print() implementations and move it to cpukit.
Update #4459.
Diffstat (limited to '')
-rw-r--r-- | cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h index a99da74fa9..a8ed0aec23 100644 --- a/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h @@ -117,6 +117,28 @@ #endif #endif +#define SPARC_REGISTER_WINDOW_OFFSET_LOCAL( i ) ( ( i ) * 4 ) +#define SPARC_REGISTER_WINDOW_OFFSET_INPUT( i ) ( ( i ) * 4 + 32 ) +#define SPARC_REGISTER_WINDOW_SIZE 64 + +#define SPARC_EXCEPTION_OFFSET_PSR 0 +#define SPARC_EXCEPTION_OFFSET_PC 4 +#define SPARC_EXCEPTION_OFFSET_NPC 8 +#define SPARC_EXCEPTION_OFFSET_TRAP 12 +#define SPARC_EXCEPTION_OFFSET_WIM 16 +#define SPARC_EXCEPTION_OFFSET_Y 20 +#define SPARC_EXCEPTION_OFFSET_GLOBAL( i ) ( ( i ) * 4 + 24 ) +#define SPARC_EXCEPTION_OFFSET_OUTPUT( i ) ( ( i ) * 4 + 56 ) +#define SPARC_EXCEPTION_OFFSET_WINDOWS( i ) ( ( i ) * 64 + 88 ) + +#if SPARC_HAS_FPU == 1 +#define SPARC_EXCEPTION_OFFSET_FSR 536 +#define SPARC_EXCEPTION_OFFSET_FP( i ) ( ( i ) * 8 + 544 ) +#define SPARC_EXCEPTION_FRAME_SIZE 672 +#else +#define SPARC_EXCEPTION_FRAME_SIZE 536 +#endif + #ifndef ASM #ifdef __cplusplus |