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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-04-22 07:46:56 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-04-28 09:26:19 +0200 |
| commit | b2ec2d15971503466e1debf596dc84b6af0f9b13 (patch) | |
| tree | 9c5ccc58cf5c957d5c21f36cd1eb5a73e899b377 /cpukit/score/cpu/sparc/cpu.c | |
| parent | score: Add _CPU_Get_current_per_CPU_control() (diff) | |
| download | rtems-b2ec2d15971503466e1debf596dc84b6af0f9b13.tar.bz2 | |
sparc: Optimize context switch
The registers g2 through g4 are reserved for applications. GCC uses
them as volatile registers by default. So they are treated like
volatile registers in RTEMS as well.
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/sparc/cpu.c | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c index 73ed4fdd78..463ff4736c 100644 --- a/cpukit/score/cpu/sparc/cpu.c +++ b/cpukit/score/cpu/sparc/cpu.c @@ -35,13 +35,20 @@ RTEMS_STATIC_ASSERT( Context_Control_offset_ ## field \ ) -SPARC_ASSERT_OFFSET(g2_g3, G2); -SPARC_ASSERT_OFFSET(g4, G4); SPARC_ASSERT_OFFSET(g5, G5); SPARC_ASSERT_OFFSET(g6, G6); SPARC_ASSERT_OFFSET(g7, G7); -SPARC_ASSERT_OFFSET(l0, L0); -SPARC_ASSERT_OFFSET(l1, L1); + +RTEMS_STATIC_ASSERT( + offsetof(Context_Control, l0_and_l1) == L0_OFFSET, + Context_Control_offset_L0 +); + +RTEMS_STATIC_ASSERT( + offsetof(Context_Control, l0_and_l1) + 4 == L1_OFFSET, + Context_Control_offset_L1 +); + SPARC_ASSERT_OFFSET(l2, L2); SPARC_ASSERT_OFFSET(l3, L3); SPARC_ASSERT_OFFSET(l4, L4); @@ -61,12 +68,6 @@ SPARC_ASSERT_OFFSET(o7, O7); SPARC_ASSERT_OFFSET(psr, PSR); SPARC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE_STACK); -RTEMS_STATIC_ASSERT( - (offsetof(Context_Control, g2_g3) - + offsetof(Context_Control, g4)) / 2 == G3_OFFSET, - Context_Control_offset_G3 -); - /* * This initializes the set of opcodes placed in each trap * table entry. The routine which installs a handler is responsible |