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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-02-25 17:45:06 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-02-25 20:38:20 +0100 |
| commit | faaffbd913c0e4e39444b2b4b0e0bfb93cc1a0a2 (patch) | |
| tree | 22e840b74ab2f28e275ade935d98116e40e3df19 /cpukit/score/cpu/riscv/riscv-exception-handler.S | |
| parent | bsps/riscv: Add missing include (diff) | |
| download | rtems-faaffbd913c0e4e39444b2b4b0e0bfb93cc1a0a2.tar.bz2 | |
riscv: Use zicsr architecture extension
This is required for ISA 2.0 support, see chapter
"Zicsr", Control and Status Register (CSR) Instructions, Version 2.0
in
RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-exception-handler.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S index 9330f246b1..87a69652a4 100644 --- a/cpukit/score/cpu/riscv/riscv-exception-handler.S +++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S @@ -45,6 +45,7 @@ PUBLIC(_RISCV_Exception_handler) .section .text, "ax", @progbits .align 2 + .option arch, +zicsr TYPE_FUNC(_RISCV_Exception_handler) SYM(_RISCV_Exception_handler): |