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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-03 09:54:47 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-05 07:12:24 +0200 |
| commit | e755782bde234350c6263f893b1c4e8d30bb0a53 (patch) | |
| tree | 996842ed7493ec8423822b9a49ea58cd26d6dc03 /cpukit/score/cpu/riscv/riscv-exception-handler.S | |
| parent | posix: Check for new <pthread.h> prototypes (diff) | |
| download | rtems-e755782bde234350c6263f893b1c4e8d30bb0a53.tar.bz2 | |
riscv: Clear reservations
See also RISC-V User-Level ISA V2.3, comment in section 8.2
"Load-Reserved/Store-Conditional Instructions".
Update #3433.
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-exception-handler.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S index b15bab49c7..05bad455ac 100644 --- a/cpukit/score/cpu/riscv/riscv-exception-handler.S +++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S @@ -115,6 +115,8 @@ SYM(ISR_Handler): sw t2, PER_CPU_ISR_NEST_LEVEL(s0) sw t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0) + CLEAR_RESERVATIONS s0 + /* Keep sp (Exception frame address) in s1 */ mv s1, sp |