diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-27 14:47:17 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-27 15:06:55 +0200 |
| commit | cfc95736ffe1d891e850ed2e702e467b3f10165e (patch) | |
| tree | 68b0526eb23595e290dcfd5666cec6c8a0333743 /cpukit/score/cpu/riscv/riscv-counter.S | |
| parent | samples/minimum: Use default interrupt stack size (diff) | |
| download | rtems-cfc95736ffe1d891e850ed2e702e467b3f10165e.tar.bz2 | |
riscv: Rework CPU counter support
Update #3433.
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-counter.S | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/riscv-counter.S b/cpukit/score/cpu/riscv/riscv-counter.S new file mode 100644 index 0000000000..e779325b4b --- /dev/null +++ b/cpukit/score/cpu/riscv/riscv-counter.S @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018 embedded brains GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#if __riscv_xlen == 32 +#define PTR_ALIGN 2 +#define PTR_SIZE 4 +#define PTR_VALUE .word +#elif __riscv_xlen == 64 +#define PTR_ALIGN 3 +#define PTR_SIZE 8 +#define PTR_VALUE .dword +#endif + + .section .sdata, "aw" + .align PTR_ALIGN + + .globl _RISCV_Counter + .type _RISCV_Counter, @object + .size _RISCV_Counter, PTR_SIZE +_RISCV_Counter: + + .globl _RISCV_Counter_mutable + .type _RISCV_Counter_mutable, @object + .size _RISCV_Counter_mutable, PTR_SIZE +_RISCV_Counter_mutable: + + PTR_VALUE _RISCV_Counter_register |