riscv: Use zicsr architecture extension

This is required for ISA 2.0 support, see chapter

"Zicsr", Control and Status Register (CSR) Instructions, Version 2.0

in

RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA

1 files changed, 7 insertions, 1 deletions

diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
index eee6ad7328..5162cbbd51 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
@@ -399,7 +399,13 @@ static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void )
 {
   struct Per_CPU_Control *cpu_self;
 
-  __asm__ volatile ( "csrr %0, mscratch" : "=r" ( cpu_self ) );
+  __asm__ volatile (
+    ".option push\n"
+    ".option arch, +zicsr\n"
+    "csrr %0, mscratch\n"
+    ".option pop" :
+    "=r" ( cpu_self )
+  );
 
   return cpu_self;
 }