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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-03 09:54:47 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-05 07:12:24 +0200 |
| commit | e755782bde234350c6263f893b1c4e8d30bb0a53 (patch) | |
| tree | 996842ed7493ec8423822b9a49ea58cd26d6dc03 /cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | |
| parent | posix: Check for new <pthread.h> prototypes (diff) | |
| download | rtems-e755782bde234350c6263f893b1c4e8d30bb0a53.tar.bz2 | |
riscv: Clear reservations
See also RISC-V User-Level ISA V2.3, comment in section 8.2
"Load-Reserved/Store-Conditional Instructions".
Update #3433.
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index 9c50be89dd..54c5cf1b79 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -34,7 +34,11 @@ #include <rtems/score/cpu.h> +#ifdef __riscv_atomic +#define CPU_PER_CPU_CONTROL_SIZE 16 +#else #define CPU_PER_CPU_CONTROL_SIZE 0 +#endif #ifdef RTEMS_SMP #define RISCV_CONTEXT_IS_EXECUTING 0 @@ -286,6 +290,13 @@ typedef struct { uintptr_t a1; } RTEMS_ALIGNED( CPU_STACK_ALIGNMENT ) CPU_Interrupt_frame; +#ifdef __riscv_atomic +typedef struct { + uint64_t clear_reservations; + uint32_t reserved_for_alignment_of_interrupt_frame[ 2 ]; +} CPU_Per_CPU_control; +#endif + static inline uint32_t _RISCV_Read_FCSR( void ) { uint32_t fcsr; |