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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-27 08:54:13 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-29 10:04:37 +0200 |
| commit | b706b4a3c09184b2f8ebf5290dc2b1d4a4db6684 (patch) | |
| tree | 70654e29a9a7af7995aa6325e42ce36de176bccf /cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | |
| parent | riscv: Remove x8 initialization (diff) | |
| download | rtems-b706b4a3c09184b2f8ebf5290dc2b1d4a4db6684.tar.bz2 | |
riscv: Remove mstatus from thread context
The mstatus register contains no thread-specific state which must be
saved/restored during a context switch. Machine interrupts (MIE) must
be enabled during a context switch.
Create separate CPU_Interrupt_frame structure.
Update #3433.
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index 6279c7c22e..4952e29537 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -38,15 +38,15 @@ #if __riscv_xlen == 32 -#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 140 +#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 128 -#define CPU_INTERRUPT_FRAME_SIZE 144 +#define CPU_INTERRUPT_FRAME_SIZE 140 #elif __riscv_xlen == 64 -#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 280 +#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 256 -#define CPU_INTERRUPT_FRAME_SIZE 288 +#define CPU_INTERRUPT_FRAME_SIZE 280 #endif /* __riscv_xlen */ @@ -56,6 +56,13 @@ extern "C" { #endif +typedef struct { + unsigned long x[32]; + unsigned long mstatus; + unsigned long mcause; + unsigned long mepc; +} CPU_Interrupt_frame; + #ifdef RTEMS_SMP static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void ) |