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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-19 12:11:19 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-25 10:07:43 +0200 |
commit | 8db3f0e878b7f008ad05716f501220509662e2c4 (patch) | |
tree | d55db59defa95096a3ef156427822a9f8744ab58 /cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | |
parent | riscv: New CPU_Exception_frame (diff) | |
download | rtems-8db3f0e878b7f008ad05716f501220509662e2c4.tar.bz2 |
riscv: Rework exception handling
Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions. Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.
Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.
Update #3433.
Diffstat (limited to '')
-rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index cb60a528de..313b671da0 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -289,6 +289,13 @@ typedef struct { } CPU_Per_CPU_control; #endif +struct Per_CPU_Control; + +void _RISCV_Interrupt_dispatch( + uintptr_t mcause, + struct Per_CPU_Control *cpu_self +); + static inline uint32_t _RISCV_Read_FCSR( void ) { uint32_t fcsr; |