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| author | Andreas Dachsberger <andreas.dachsberger@embedded-brains.de> | 2019-03-27 10:38:56 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2019-04-02 07:29:30 +0200 |
| commit | 71f90982dc217815ab873698b1852640b9d66534 (patch) | |
| tree | 61acd34a5e703d5656d0bdd99a856a8dea3112c9 /cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | |
| parent | doxygen: score: Add powerpc CPU architecture group (diff) | |
| download | rtems-71f90982dc217815ab873698b1852640b9d66534.tar.bz2 | |
doxygen: score: Add RISC-V CPU architecture group
Update #3706.
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index 5a256e8b75..c381cce110 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -34,6 +34,16 @@ #include <rtems/score/cpu.h> +/** + * @defgroup RTEMSScoreCPURISCV RISC-V + * + * @ingroup RTEMSScoreCPU + * + * @brief RISCV Architecture Support + * + * @{ + */ + #if defined(__riscv_atomic) && __riscv_xlen == 64 #define CPU_PER_CPU_CONTROL_SIZE 48 #elif defined(__riscv_atomic) && __riscv_xlen == 32 @@ -418,4 +428,6 @@ RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) #endif /* ASM */ +/** @} */ + #endif /* _RTEMS_SCORE_CPUIMPL_H */ |