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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-05-11 06:54:59 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-28 15:02:12 +0200 |
| commit | 2086948a7b06ac238c4ff0c9263c1e578e900fdd (patch) | |
| tree | 8d80d467e4636af6ac211406557f6d8e4be0f0ae /cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | |
| parent | build: Enable RISC-V SMP build (diff) | |
| download | rtems-2086948a7b06ac238c4ff0c9263c1e578e900fdd.tar.bz2 | |
riscv: Add dummy SMP support
Update #3433.
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index 3904c84bf9..2a63e03513 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -5,7 +5,7 @@ */ /* - * Copyright (c) 2013 embedded brains GmbH + * Copyright (c) 2013, 2018 embedded brains GmbH * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -36,6 +36,16 @@ #define CPU_PER_CPU_CONTROL_SIZE 0 +#if __riscv_xlen == 32 + +#define CPU_INTERRUPT_FRAME_SIZE 144 + +#elif __riscv_xlen == 64 + +#define CPU_INTERRUPT_FRAME_SIZE 288 + +#endif /* __riscv_xlen */ + #ifndef ASM #ifdef __cplusplus |