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authorSebastian Huber <sebastian.huber@embedded-brains.de>2018-06-19 14:59:51 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2018-06-27 08:58:16 +0200
commitc8df844cf3bddde0221614843c97cb6c950cdba9 (patch)
tree67101cb39d5bdd406f785d33629703e5a876ed75 /cpukit/score/cpu/riscv/include/rtems/score/cpu.h
parentconsole: Add missing return status (diff)
downloadrtems-c8df844cf3bddde0221614843c97cb6c950cdba9.tar.bz2
score: Add CPU_INTERRUPT_STACK_ALIGNMENT
Add CPU port define for the interrupt stack alignment. The alignment should take the stack ABI and the cache line size into account. Update #3459.
Diffstat (limited to 'cpukit/score/cpu/riscv/include/rtems/score/cpu.h')
-rw-r--r--cpukit/score/cpu/riscv/include/rtems/score/cpu.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index 663dd090f2..2b3b60937e 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -137,6 +137,8 @@ typedef Context_Control CPU_Interrupt_frame;
#define CPU_CONTEXT_FP_SIZE 0
Context_Control_fp _CPU_Null_fp_context;
+#define CPU_CACHE_LINE_BYTES 64
+
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
#if __riscv_xlen == 32
#define CPU_STACK_MINIMUM_SIZE 4096
@@ -148,6 +150,9 @@ Context_Control_fp _CPU_Null_fp_context;
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
#define CPU_STACK_ALIGNMENT 8
+
+#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
+
#define _CPU_Initialize_vectors()
/*