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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-27 08:35:13 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-29 10:04:36 +0200 |
commit | 9510742e7ff48c3df177ec9f7b5e0d229c696e85 (patch) | |
tree | 2a2eeee5ee75dbc0823e90b5d9ab3feec75887bd /cpukit/score/cpu/riscv/include/rtems/score/cpu.h | |
parent | riscv: Remove RISCV_GCC_RED_ZONE_SIZE (diff) | |
download | rtems-9510742e7ff48c3df177ec9f7b5e0d229c696e85.tar.bz2 |
riscv: Fix CPU_STACK_ALIGNMENT
According to the RISC-V psABI
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
the stack alignment is 128 bits (16 bytes).
Update #3433.
Diffstat (limited to '')
-rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 564812c246..9a628c04ca 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -107,7 +107,8 @@ Context_Control_fp _CPU_Null_fp_context; #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT -#define CPU_STACK_ALIGNMENT 8 + +#define CPU_STACK_ALIGNMENT 16 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |