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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-22 13:30:49 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-28 15:02:08 +0200 |
commit | 7c3b0df10752cc4bdd1175f5b16fd0978763ff46 (patch) | |
tree | b3fa7df13c2d4e8c89fc95859e25a91928243f58 /cpukit/score/cpu/riscv/include/rtems/score/cpu.h | |
parent | bsp/riscv: Load global pointer (diff) | |
download | rtems-7c3b0df10752cc4bdd1175f5b16fd0978763ff46.tar.bz2 |
riscv: Implement ISR set/get level
Fix prototypes.
Update #3433.
Diffstat (limited to '')
-rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 1e72dd3709..d70db39b85 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -187,9 +187,20 @@ RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level ) return ( level & MSTATUS_MIE ) != 0; } -void _CPU_ISR_Set_level( unsigned long level ); +RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level( uint32_t level ) +{ + if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) { + __asm__ volatile ( + "csrrs zero, mstatus, " RTEMS_XSTRING( MSTATUS_MIE ) + ); + } else { + __asm__ volatile ( + "csrrc zero, mstatus, " RTEMS_XSTRING( MSTATUS_MIE ) + ); + } +} -unsigned long _CPU_ISR_Get_level( void ); +uint32_t _CPU_ISR_Get_level( void ); /* end of ISR handler macros */ |