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authorSebastian Huber <sebastian.huber@embedded-brains.de>2017-06-20 10:39:54 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2017-06-20 10:41:39 +0200
commitae3e6af82aa07caa9584ac5f8078a721746efda5 (patch)
tree9b57322339620485cd288315d12bbe612096fff6 /cpukit/score/cpu/powerpc/rtems/score
parentbsps: Improve interrupt vector enable/disable API (diff)
downloadrtems-ae3e6af82aa07caa9584ac5f8078a721746efda5.tar.bz2
powerpc: Fix TLS support
Do not zero the GPR2 in the thread context via dcbz instructions. Bug was introduced by 32b4a0c42704f0076da8e2d5411290f55d1b2965.
Diffstat (limited to 'cpukit/score/cpu/powerpc/rtems/score')
-rw-r--r--cpukit/score/cpu/powerpc/rtems/score/cpu.h21
1 files changed, 11 insertions, 10 deletions
diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/rtems/score/cpu.h
index f9a43b18b8..53b4bd21fa 100644
--- a/cpukit/score/cpu/powerpc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/powerpc/rtems/score/cpu.h
@@ -222,8 +222,8 @@ typedef struct {
PPC_GPR_TYPE gpr29;
PPC_GPR_TYPE gpr30;
PPC_GPR_TYPE gpr31;
- uint32_t gpr2;
uint32_t isr_dispatch_disable;
+ uint32_t reserved_for_alignment;
#if defined(PPC_MULTILIB_ALTIVEC)
uint8_t v20[16];
uint8_t v21[16];
@@ -270,12 +270,13 @@ typedef struct {
double f30;
double f31;
#endif
+ /*
+ * The following items are at the structure end, so that we can use dcbz for
+ * the previous items to optimize the context switch. We must not set the
+ * following items to zero via the dcbz.
+ */
+ uint32_t gpr2;
#if defined(RTEMS_SMP)
- /*
- * This item is at the structure end, so that we can use dcbz for the
- * previous items to optimize the context switch. We must not set this
- * item to zero via the dcbz.
- */
volatile uint32_t is_executing;
#endif
} ppc_context;
@@ -347,9 +348,7 @@ static inline ppc_context *ppc_get_context( const Context_Control *context )
#define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 )
#define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 )
#define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 )
-#define PPC_CONTEXT_OFFSET_GPR2 PPC_CONTEXT_GPR_OFFSET( 32 )
-#define PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE \
- ( PPC_CONTEXT_GPR_OFFSET( 32 ) + 4 )
+#define PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE PPC_CONTEXT_GPR_OFFSET( 32 )
#ifdef PPC_MULTILIB_ALTIVEC
#define PPC_CONTEXT_OFFSET_V( v ) \
@@ -403,8 +402,10 @@ static inline ppc_context *ppc_get_context( const Context_Control *context )
#define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8)
#endif
+#define PPC_CONTEXT_OFFSET_GPR2 PPC_CONTEXT_VOLATILE_SIZE
+
#ifdef RTEMS_SMP
- #define PPC_CONTEXT_OFFSET_IS_EXECUTING PPC_CONTEXT_VOLATILE_SIZE
+ #define PPC_CONTEXT_OFFSET_IS_EXECUTING (PPC_CONTEXT_VOLATILE_SIZE + 4)
#endif
#ifndef ASM