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| author | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2009-02-27 11:06:21 +0000 |
|---|---|---|
| committer | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2009-02-27 11:06:21 +0000 |
| commit | cd4ed384229a8dd7484ca571a2963ad33f14da48 (patch) | |
| tree | 3fe49de1d212a39b53b3062604dd367964770498 /cpukit/score/cpu/powerpc/ChangeLog | |
| parent | * libmisc/shell/shell.c, libmisc/shell/shell.h: Changed type for (diff) | |
| download | rtems-cd4ed384229a8dd7484ca571a2963ad33f14da48.tar.bz2 | |
* rtems/powerpc/registers.h: Added Freescale Book E Implementation
Standards (EIS) special purpose register definitions for MMU and L1
cache.
Diffstat (limited to 'cpukit/score/cpu/powerpc/ChangeLog')
| -rw-r--r-- | cpukit/score/cpu/powerpc/ChangeLog | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/cpukit/score/cpu/powerpc/ChangeLog b/cpukit/score/cpu/powerpc/ChangeLog index feb98cd9ee..f0eba118d4 100644 --- a/cpukit/score/cpu/powerpc/ChangeLog +++ b/cpukit/score/cpu/powerpc/ChangeLog @@ -1,3 +1,9 @@ +2009-02-27 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/powerpc/registers.h: Added Freescale Book E Implementation + Standards (EIS) special purpose register definitions for MMU and L1 + cache. + 2009-02-11 Joel Sherrill <joel.sherrill@oarcorp.com> * rtems/new-exceptions/cpu.h, rtems/score/cpu.h: Eliminate |