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| author | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2008-07-11 10:04:40 +0000 |
|---|---|---|
| committer | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2008-07-11 10:04:40 +0000 |
| commit | 767cdd8470eac9396d326a65f640e5234784a3d4 (patch) | |
| tree | b226e9649661dfd1b7e7fb209ed19b5bfb548d4e /cpukit/score/cpu/powerpc/ChangeLog | |
| parent | add display driver for HCMS* SPI displays (diff) | |
| download | rtems-767cdd8470eac9396d326a65f640e5234784a3d4.tar.bz2 | |
adapted for modified exception code
Diffstat (limited to 'cpukit/score/cpu/powerpc/ChangeLog')
| -rw-r--r-- | cpukit/score/cpu/powerpc/ChangeLog | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/cpukit/score/cpu/powerpc/ChangeLog b/cpukit/score/cpu/powerpc/ChangeLog index bb7cd0bd03..431492b5a7 100644 --- a/cpukit/score/cpu/powerpc/ChangeLog +++ b/cpukit/score/cpu/powerpc/ChangeLog @@ -1,3 +1,24 @@ +2008-07-10 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/asm.h: Added defines for save and restore registers and + special purpose registers 4 to 7. + + * rtems/new-exceptions/cpu.h: Changed define PPC_BSP_HAS_FIXED_PR288 to + a value that results in a compile time error on usage since SPRG0 is + now used for the interrupt disable mask. + + * rtems/powerpc/registers.h: Bugfix: Swapped values of TBWU and TBWL. + + Added defines SPRG4..7 and USPRG0. + + Changed _CPU_ISR_{Disable, Enable, Flush} to use static inline + functions. The interrupt disable mask is now stored in SPRG0. Which + was previously denoted to indicate a PR288 bugfix. You may now + initialize the interrupt disable mask via + ppc_interrupt_set_disable_mask() and + PPC_INTERRUPT_DISABLE_MASK_DEFAULT. The default value will be set in + bootcard.c. + 2008-02-20 Ralf Corsépius <ralf.corsepius@rtems.org> * rtems/old-exceptions/cpu.h: Remove (Abandoned). |