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authorSebastian Huber <sebastian.huber@embedded-brains.de>2022-09-08 10:37:05 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2022-09-19 09:09:22 +0200
commita660e9dc47c522fe1a1b7f6e4af1795dbd6c20b1 (patch)
tree390cdbf3680f7549dc30fa78747f733c6010cb1e /cpukit/score/cpu/no_cpu/include
parentvalidation: Test deadlock detection special case (diff)
downloadrtems-a660e9dc47c522fe1a1b7f6e4af1795dbd6c20b1.tar.bz2
Do not use RTEMS_INLINE_ROUTINE
Directly use "static inline" which is available in C99 and later. This brings the RTEMS implementation closer to standard C. Close #3935.
Diffstat (limited to 'cpukit/score/cpu/no_cpu/include')
-rw-r--r--cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h2
-rw-r--r--cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h6
2 files changed, 4 insertions, 4 deletions
diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
index 63829b5272..962fc486fc 100644
--- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
@@ -695,7 +695,7 @@ extern Context_Control_fp _CPU_Null_fp_context;
* @retval true Interrupts are enabled in the ISR level.
* @retval false Otherwise.
*/
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return false;
}
diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
index 1eec4e6b7a..d5082383e8 100644
--- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
@@ -151,7 +151,7 @@ void _CPU_Context_validate( uintptr_t pattern );
*
* This function is used only in test sptests/spfatal26.
*/
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( ".word 0" );
}
@@ -161,7 +161,7 @@ RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
*
* This function is used only in test sptests/spcache01.
*/
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
@@ -176,7 +176,7 @@ RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
* @param context is the processor context defining the thread-local storage
* area to use.
*/
-RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage(
+static inline void _CPU_Use_thread_local_storage(
const Context_Control *context
)
{