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authorJoel Sherrill <joel.sherrill@OARcorp.com>2008-06-05 14:30:07 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2008-06-05 14:30:07 +0000
commit2fd427c7926495b3e1ad3c7aaaa489f8cde95573 (patch)
tree7ff7f4fc896909274f626ceaf23693571cf3cd4e /cpukit/score/cpu/mips/rtems/score/cpu.h
parent2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com> (diff)
downloadrtems-2fd427c7926495b3e1ad3c7aaaa489f8cde95573.tar.bz2
2008-06-05 Joel Sherrill <joel.sherrill@OARcorp.com>
* rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting parameter to indicate that the port uses the Simple Vectored Interrupt model or the Programmable Interrupt Controller Model. The PIC model is implemented primarily in the BSP and it is responsible for all memory allocation.
Diffstat (limited to '')
-rw-r--r--cpukit/score/cpu/mips/rtems/score/cpu.h14
1 files changed, 13 insertions, 1 deletions
diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h
index 863866fc3d..7c676d2a4a 100644
--- a/cpukit/score/cpu/mips/rtems/score/cpu.h
+++ b/cpukit/score/cpu/mips/rtems/score/cpu.h
@@ -124,6 +124,19 @@ extern "C" {
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
/*
+ * Does the CPU follow the simple vectored interrupt model?
+ *
+ * If TRUE, then RTEMS allocates the vector table it internally manages.
+ * If FALSE, then the BSP is assumed to allocate and manage the vector
+ * table
+ *
+ * MIPS Specific Information:
+ *
+ * XXX document implementation including references if appropriate
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+
+/*
* Does this CPU have hardware support for a dedicated interrupt stack?
*
* If TRUE, then it must be installed during initialization.
@@ -675,7 +688,6 @@ extern unsigned int mips_interrupt_number_of_vectors;
#define CPU_STACK_MINIMUM_SIZE (8 * 1024)
-
/*
* CPU's worst alignment requirement for data types on a byte boundary. This
* alignment does not take into account the requirements for the stack.