diff options
| author | Jennifer Averett <jennifer.averett@OARcorp.com> | 2012-04-04 08:39:46 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@oarcorp.com> | 2012-04-04 08:43:08 -0500 |
| commit | 0c0181dee26d64835f0cd4f47ef81f681ea553e8 (patch) | |
| tree | 2f8aef096fa1ed345176328b805d9bb8394fd2f8 /cpukit/score/cpu/mips/rtems/score/cpu.h | |
| parent | bsp/mpc55xx: Add and use chip features (diff) | |
| download | rtems-0c0181dee26d64835f0cd4f47ef81f681ea553e8.tar.bz2 | |
PR 1993 - Convert MIPS to PIC IRQ model
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/mips/rtems/score/cpu.h | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h index f626636dab..8215d346b5 100644 --- a/cpukit/score/cpu/mips/rtems/score/cpu.h +++ b/cpukit/score/cpu/mips/rtems/score/cpu.h @@ -1,4 +1,6 @@ -/* +/** + * @file + * * Mips CPU Dependent Header File * * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and @@ -12,6 +14,9 @@ * added the new interrupt vectoring support in libcpu and * tried to better support the various interrupt controllers. * + */ + +/* * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> * COPYRIGHT (c) 1996 by Transition Networks Inc. * @@ -26,13 +31,13 @@ * Transition Networks makes no representations about the suitability * of this software for any purpose. * - * COPYRIGHT (c) 1989-2006. + * COPYRIGHT (c) 1989-2012. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. - * + * * $Id$ */ @@ -124,7 +129,7 @@ extern "C" { * * XXX document implementation including references if appropriate */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE +#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE /* * Does this CPU have hardware support for a dedicated interrupt stack? @@ -201,9 +206,13 @@ extern "C" { * In this case, this option should be TRUE. * * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. + * + * Mips Note: It appears the GCC can implicitly generate FPU + * and Altivec instructions when you least expect them. So make + * all tasks floating point. */ -#define CPU_ALL_TASKS_ARE_FP FALSE +#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP /* * Should the IDLE task have a floating point context? |