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authorAlex Ivanov <alexivanov97@gmail.com>2012-11-30 15:34:17 -0600
committerJoel Sherrill <joel.sherrill@oarcorp.com>2012-11-30 15:35:36 -0600
commite0f91da505b5c907b545016645c07a3132696236 (patch)
treea3cbe53af4f52687425266b19082eb42ce34218b /cpukit/score/cpu/mips/cpu.c
parent4a7dc83762e198263f5186695d2f7ffe41ec8cba (diff)
downloadrtems-e0f91da505b5c907b545016645c07a3132696236.tar.bz2
score misc: Score misc: Clean up Doxygen #9 (GCI 2012)
This patch is a task from GCI 2012 which improves the Doxygen comments in the RTEMS source. https://google-melange.appspot.com/gci/task/view/google/gci2012/7977211
Diffstat (limited to '')
-rw-r--r--cpukit/score/cpu/mips/cpu.c46
1 files changed, 7 insertions, 39 deletions
diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c
index 657e53e071..5f7abeb368 100644
--- a/cpukit/score/cpu/mips/cpu.c
+++ b/cpukit/score/cpu/mips/cpu.c
@@ -1,7 +1,11 @@
/**
* @file
- *
- * Mips CPU Dependent Source
+ *
+ * @brief MIPS CPU Dependent Source
+ */
+
+/*
+ * MIPS CPU Dependent Source
*
* 2002: Greg Menke (gregory.menke@gsfc.nasa.gov)
* Overhauled interrupt level and interrupt enable/disable code
@@ -19,9 +23,7 @@
* wrote the JMR3904 BSP so this could be tested. Joel also
* added the new interrupt vectoring support in libcpu and
* tried to better support the various interrupt controllers.
- */
-
-/*
+ *
* Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
* COPYRIGHT (c) 1996 by Transition Networks Inc.
*
@@ -65,10 +67,6 @@ typedef uint64_t ESF_PTR_TYPE;
#endif
ESF_PTR_TYPE __exceptionStackFrame = 0;
-
-
-
-
/* _CPU_Initialize
*
* This routine performs processor dependent initialization.
@@ -93,12 +91,6 @@ void _CPU_Initialize(void)
#endif
}
-/*
- * _CPU_ISR_Get_level
- *
- * This routine returns the current interrupt level.
- */
-
uint32_t _CPU_ISR_Get_level( void )
{
unsigned int sr;
@@ -120,8 +112,6 @@ uint32_t _CPU_ISR_Get_level( void )
#endif
return sr;
}
-
-
void _CPU_ISR_Set_level( uint32_t new_level )
{
unsigned int sr, srbits;
@@ -172,31 +162,11 @@ void _CPU_ISR_Set_level( uint32_t new_level )
mips_set_sr( sr );
}
-/*
- * _CPU_Install_interrupt_stack
- */
-
void _CPU_Install_interrupt_stack( void )
{
/* we don't support this yet */
}
-/*
- * _CPU_Context_Initialize
- *
- * This kernel routine initializes the basic non-FP context area associated
- * with each thread.
- *
- * Input parameters:
- * the_context - pointer to the context area
- * stack_base - address of memory for the SPARC
- * size - size in bytes of the stack area
- * new_level - interrupt level for this context area
- * entry_point - the starting execution point for this this context
- * is_fp - TRUE if this context is associated with an FP thread
- *
- * Output parameters: NONE
- */
void _CPU_Context_Initialize(
Context_Control *the_context,
uintptr_t *stack_base,
@@ -222,8 +192,6 @@ void _CPU_Context_Initialize(
((intlvl & 1)?_INTON:0)) ) |
SR_CU0 | ((is_fp)?SR_CU1:0) | _EXTRABITS;
}
-
-
/*
* _CPU_Internal_threads_Idle_thread_body
*