diff options
| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2004-04-09 14:52:40 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2004-04-09 14:52:40 +0000 |
| commit | c18134552a66037e894b1a11060dd59883950558 (patch) | |
| tree | 8ed7f81438895cb598ec2caa43454ad3d93c9c5a /cpukit/score/cpu/mips/cpu.c | |
| parent | 2004-04-09 Joel Sherrill <joel@OARcorp.com> (diff) | |
| download | rtems-c18134552a66037e894b1a11060dd59883950558.tar.bz2 | |
2004-04-09 Joel Sherrill <joel@OARcorp.com>
PR 605/bsps
* cpu.c: Do not use C++ style comments.
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/mips/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c index 50904f9371..2c601c693d 100644 --- a/cpukit/score/cpu/mips/cpu.c +++ b/cpukit/score/cpu/mips/cpu.c @@ -99,7 +99,7 @@ uint32_t _CPU_ISR_Get_level( void ) mips_get_sr(sr); - //printf("current sr=%08X, ",sr); + /* printf("current sr=%08X, ",sr); */ #if __mips == 3 /* EXL bit and shift down hardware ints into bits 1 thru 6 */ @@ -112,7 +112,7 @@ uint32_t _CPU_ISR_Get_level( void ) #else #error "CPU ISR level: unknown MIPS level for SR handling" #endif - //printf("intlevel=%02X\n",sr); + /* printf("intlevel=%02X\n",sr); */ return sr; } |