summaryrefslogtreecommitdiffstats
path: root/cpukit/score/cpu/mips/cpu.c
diff options
context:
space:
mode:
authorGreg Menke <gregory.menke@gsfc.nasa.gov>2006-06-08 18:03:55 +0000
committerGreg Menke <gregory.menke@gsfc.nasa.gov>2006-06-08 18:03:55 +0000
commit7c990076419ff4a80999dcc04985688cd5bea5ce (patch)
tree5199f71be51bf7f51705f85683cd0f9aa4a5765d /cpukit/score/cpu/mips/cpu.c
parent549e88f62312dd972d0b1c9353999611404934bd (diff)
downloadrtems-7c990076419ff4a80999dcc04985688cd5bea5ce.tar.bz2
B.Robinson MIPS patch
Diffstat (limited to '')
-rw-r--r--cpukit/score/cpu/mips/cpu.c21
1 files changed, 14 insertions, 7 deletions
diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c
index 7ce5d685ec..3d11aaa275 100644
--- a/cpukit/score/cpu/mips/cpu.c
+++ b/cpukit/score/cpu/mips/cpu.c
@@ -50,11 +50,18 @@
/*
-** local dword used in cpu_asm to pass the exception stack frame to the
-** context switch code.
+** Exception stack frame pointer used in cpu_asm to pass the exception stack frame
+** address to the context switch code.
*/
-unsigned __exceptionStackFrame = 0;
+#if (__mips == 1)
+typedef uint32_t ESF_PTR_TYPE;
+#elif (__mips == 3)
+typedef uint64_t ESF_PTR_TYPE;
+#else
+#error "unknown MIPS ISA"
+#endif
+ESF_PTR_TYPE __exceptionStackFrame = 0;
@@ -107,11 +114,11 @@ uint32_t _CPU_ISR_Get_level( void )
#if (__mips == 3) || (__mips == 32)
/* IE bit and shift down hardware ints into bits 1 thru 6 */
- sr = (sr & SR_IE) | ((sr & 0xfc00) >> 9);
+ sr = (sr & SR_IE) | ((sr & mips_interrupt_mask()) >> 9);
#elif __mips == 1
/* IEC bit and shift down hardware ints into bits 1 thru 6 */
- sr = (sr & SR_IEC) | ((sr & 0xfc00) >> 9);
+ sr = (sr & SR_IEC) | ((sr & mips_interrupt_mask()) >> 9);
#else
#error "CPU ISR level: unknown MIPS level for SR handling"
@@ -142,8 +149,8 @@ void _CPU_ISR_Set_level( uint32_t new_level )
srbits = sr & ~(0xfc00 | SR_IE);
- sr = srbits | ((new_level==0)? (0xfc00 | SR_IE): \
- (((new_level<<9) & 0xfc00) | \
+ sr = srbits | ((new_level==0)? (mips_interrupt_mask() | SR_IE): \
+ (((new_level<<9) & mips_interrupt_mask()) | \
((new_level & 1)?SR_IE:0)));
/*
if ( (new_level & SR_EXL) == (sr & SR_EXL) )