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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-12-13 18:09:48 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-12-13 18:09:48 +0000 |
commit | 32f415dc501f53c52189bc632eb337560dd90ae9 (patch) | |
tree | d1874fcede6df8f9693fe6a87c061149db3c2747 /cpukit/score/cpu/mips/cpu.c | |
parent | 2000-12-12 Jake Janovetz <janovetz@uiuc.edu> (diff) | |
download | rtems-32f415dc501f53c52189bc632eb337560dd90ae9.tar.bz2 |
2000-12-13 Joel Sherrill <joel@OARcorp.com>
* cpu_asm.h: Removed.
* Makefile.am: Remove cpu_asm.h.
* rtems/score/mips64orion.h: Renamed mips.h.
* rtems/score/mips.h: New file, formerly mips64orion.h.
Header rewritten.
(mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
mips_disable_in_interrupt_mask): New macros.
* rtems/score/Makefile.am: Reflect renaming mips64orion.h.
* asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
few defines that were in <cpu_asm.h>.
* cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
MIPS ISA 3 is still in assembly for now.
(_CPU_Thread_Idle_body): Rewrote in C.
* cpu_asm.S: Rewrote file header.
(FRAME,ENDFRAME) now in asm.h.
(_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
(_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
(_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
leaves other bits in SR alone on task switch.
(mips_enable_interrupts,mips_disable_interrupts,
mips_enable_global_interrupts,mips_disable_global_interrupts,
disable_int, enable_int): Removed.
(mips_get_sr): Rewritten as C macro.
(_CPU_Thread_Idle_body): Rewritten in C.
(init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
placed in libcpu.
(exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
to libcpu/mips/shared/interrupts.
(general): Cleaned up comment blocks and #if 0 areas.
* idtcpu.h: Made ifdef report an error.
* iregdef.h: Removed warning.
* rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
number defined by libcpu.
(_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
to access SR.
(_CPU_ISR_Set_level): Rewritten as macro for ISA I.
(_CPU_Context_Initialize): Honor ISR level in task initialization.
(_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
Diffstat (limited to '')
-rw-r--r-- | cpukit/score/cpu/mips/cpu.c | 37 |
1 files changed, 25 insertions, 12 deletions
diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c index db9ae911b4..22d66c95c0 100644 --- a/cpukit/score/cpu/mips/cpu.c +++ b/cpukit/score/cpu/mips/cpu.c @@ -66,8 +66,7 @@ void _CPU_Initialize( { unsigned int i = ISR_NUMBER_OF_VECTORS; - while ( i-- ) - { + while ( i-- ) { _ISR_Vector_table[i] = (ISR_Handler_entry)null_handler; } @@ -100,15 +99,25 @@ void _CPU_Initialize( /*PAGE * * _CPU_ISR_Get_level + * + * This routine returns the current interrupt level. */ - -#if 0 /* located in cpu_asm.S */ + +#if __mips == 3 + +/* in cpu_asm.S for now */ + +#elif __mips == 1 unsigned32 _CPU_ISR_Get_level( void ) { - /* - * This routine returns the current interrupt level. - */ + unsigned int sr; + + mips_get_sr(sr); + + return ((sr & SR_IEC) ? 0 : 1); } +#else +#error "CPU ISR level: unknown MIPS level for SR handling" #endif /*PAGE @@ -200,14 +209,18 @@ void _CPU_Install_interrupt_stack( void ) * hook with caution. */ -#if 0 /* located in cpu_asm.S */ void _CPU_Thread_Idle_body( void ) { - - for( ; ; ) - /* insert your "halt" instruction here */ ; -} +#if __mips == 3 + for( ; ; ) + asm volatile("wait"); /* use wait to enter low power mode */ +#elif __mips == 1 + for( ; ; ) + ; +#else +#error "IDLE: __mips not set to 1 or 3" #endif +} extern void mips_break( int error ); |