2001-03-13 Joel Sherrill <joel@OARcorp.com>

	* cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
	Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
	Also reimplemented some assembly routines in C further reducing
	the amount of assembly and increasing maintainability.

1 files changed, 43 insertions, 5 deletions

diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c
index 42d9807cc0..990b6b275a 100644
--- a/cpukit/score/cpu/mips/cpu.c
+++ b/cpukit/score/cpu/mips/cpu.c
@@ -90,23 +90,61 @@ void _CPU_Initialize(
  *  This routine returns the current interrupt level.
  */
    
-#if __mips == 3
-
-/* in cpu_asm.S for now */
-
-#elif __mips == 1
 unsigned32 _CPU_ISR_Get_level( void )
 {
   unsigned int sr;
 
   mips_get_sr(sr);
 
+#if __mips == 3
+  return ((sr & SR_EXL) >> 1);
+
+#elif __mips == 1
   return ((sr & SR_IEC) ? 0 : 1);
+
+#else
+#error "CPU ISR level: unknown MIPS level for SR handling"
+#endif
 }
+
+void _CPU_ISR_Set_level( unsigned32 new_level )
+{
+  unsigned int sr;
+
+  mips_get_sr(sr);
+
+#if __mips == 3
+  if ( (new_level & SR_EXL) == (sr & SR_EXL) )
+    return;
+
+  if ( (new_level & SR_EXL) == 0 ) {
+    sr &= ~SR_EXL;                    /* clear the EXL bit */
+    mips_set_sr(sr);
+  } else {
+    sr &= ~SR_IE;
+    mips_set_sr(sr);                 /* first disable ie bit (recommended) */
+
+    sr |= SR_EXL|SR_IE;              /* enable exception level */
+    mips_set_sr(sr);                 /* first disable ie bit (recommended) */
+  }
+ 
+#elif __mips == 1
+
+  if ( (new_level & SR_IEC) == (sr & SR_IEC) )
+    return;
+
+  sr &= ~SR_IEC;                    /* clear the IEC bit */
+  if ( !new_level )
+    sr |= SR_IEC;                   /* enable interrupts */
+
+  mips_set_sr(sr);
+
 #else
 #error "CPU ISR level: unknown MIPS level for SR handling"
 #endif
 
+}
+
 /*PAGE
  *
  *  _CPU_ISR_install_raw_handler