diff options
author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2022-01-26 10:56:54 -0600 |
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committer | Joel Sherrill <joel@rtems.org> | 2022-02-04 11:30:59 -0600 |
commit | ace9955fc4afc5c8f49f1ae7983aaf704f2cbbc8 (patch) | |
tree | 0f857ad469f01719c0672f57d49fbcbbf0ecc861 /cpukit/score/cpu/microblaze/include/rtems/score/cpu.h | |
parent | cpukit/microblaze: Add debug vector and handler (diff) | |
download | rtems-ace9955fc4afc5c8f49f1ae7983aaf704f2cbbc8.tar.bz2 |
cpukit/microblaze: Add exception extensions
Add the functions necessary to support RTEMS_EXCEPTION_EXTENSIONS and
mark this functionality as available on MicroBlaze.
Diffstat (limited to '')
-rw-r--r-- | cpukit/score/cpu/microblaze/include/rtems/score/cpu.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h index fe0d9a8996..5ca0609e91 100644 --- a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h @@ -194,6 +194,10 @@ typedef struct { #define MICROBLAZE_MSR_C ( 1 << 2 ) #define MICROBLAZE_MSR_IE ( 1 << 1 ) +#define MICROBLAZE_ESR_DS ( 1 << 12 ) +#define MICROBLAZE_ESR_EC_MASK 0x1f +#define MICROBLAZE_ESR_ESS_MASK 0x7f +#define MICROBLAZE_ESR_ESS_SHIFT 5 #define _CPU_MSR_GET( _msr_value ) \ do { \ @@ -358,6 +362,40 @@ void _CPU_Context_switch( Context_Control *heir ); +/* Selects the appropriate resume function based on CEF state */ +RTEMS_NO_RETURN void _CPU_Exception_resume( CPU_Exception_frame *frame ); + +RTEMS_NO_RETURN void _MicroBlaze_Exception_resume_from_exception( + CPU_Exception_frame *frame +); + +RTEMS_NO_RETURN void _MicroBlaze_Exception_resume_from_break( + CPU_Exception_frame *frame +); + +/* + * Only functions for exception cases since debug exception frames will never + * need dispatch + */ +RTEMS_NO_RETURN void _CPU_Exception_dispatch_and_resume( + CPU_Exception_frame *frame +); + +void _CPU_Exception_disable_thread_dispatch( void ); + +int _CPU_Exception_frame_get_signal( CPU_Exception_frame *frame ); + +void _CPU_Exception_frame_set_resume( + CPU_Exception_frame *frame, + void *address +); + +void _CPU_Exception_frame_make_resume_next_instruction( + CPU_Exception_frame *frame +); + +uint32_t *_MicroBlaze_Get_return_address( CPU_Exception_frame *ef ); + RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context ); |