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authorJoel Sherrill <joel.sherrill@OARcorp.com>1995-09-19 18:32:18 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>1995-09-19 18:32:18 +0000
commit38ffa0cee29a03a2158fb7d020986743c0f3bc07 (patch)
tree00efaa165f7efaadb3394b630bdf9d241d96286c /cpukit/score/cpu/m68k
parent3652ad356bf13abe0963c992cbbda96476d31609 (diff)
downloadrtems-38ffa0cee29a03a2158fb7d020986743c0f3bc07.tar.bz2
Incorporated the submission from John S. Gwynne
<jsg@coulomb.eng.ohio-state.edu> of the rest of the 68000-ish support for interrupt handling and bfffo support, the two BSPs he submitted (efi68k and efi332), and SGI Irix 5.3 host support.
Diffstat (limited to 'cpukit/score/cpu/m68k')
-rw-r--r--cpukit/score/cpu/m68k/cpu.c46
-rw-r--r--cpukit/score/cpu/m68k/qsm.h206
-rw-r--r--cpukit/score/cpu/m68k/rtems/m68k/qsm.h206
-rw-r--r--cpukit/score/cpu/m68k/rtems/m68k/sim.h325
-rw-r--r--cpukit/score/cpu/m68k/sim.h325
5 files changed, 1086 insertions, 22 deletions
diff --git a/cpukit/score/cpu/m68k/cpu.c b/cpukit/score/cpu/m68k/cpu.c
index fdba64bffe..a6d6750a5f 100644
--- a/cpukit/score/cpu/m68k/cpu.c
+++ b/cpukit/score/cpu/m68k/cpu.c
@@ -1,5 +1,5 @@
/*
- * Motorola MC68020 Dependent Source
+ * Motorola MC68xxx Dependent Source
*
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
* On-Line Applications Research Corporation (OAR).
@@ -32,9 +32,7 @@ void _CPU_Initialize(
void (*thread_dispatch) /* ignored on this CPU */
)
{
-
_CPU_Table = *cpu_table;
-
}
/*PAGE
@@ -66,9 +64,13 @@ void _CPU_ISR_install_raw_handler(
m68k_get_vbr( interrupt_table );
+#if ( M68K_HAS_VBR == 1)
*old_handler = interrupt_table[ vector ];
-
interrupt_table[ vector ] = new_handler;
+#else
+ *old_handler = *(proc_ptr *)( (int)interrupt_table+ (int)vector*6-10);
+ *(proc_ptr *)( (int)interrupt_table+ (int)vector*6-10) = new_handler;
+#endif /* M68K_HAS_VBR */
}
/*PAGE
@@ -120,24 +122,24 @@ void _CPU_Install_interrupt_stack( void )
#if ( M68K_HAS_BFFFO != 1 )
/*
- * Returns log2(x) 0<x<256
+ * Returns table for duplication of the BFFFO instruction (16 bits only)
*/
-const unsigned char __log2table[256] = {
- 0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
- 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
- 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
- 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
- 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
- 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
- 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
- 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
- 7, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
- 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
- 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
- 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
- 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
- 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
- 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,
- 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0
+const unsigned char __BFFFOtable[256] = {
+ 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
#endif
diff --git a/cpukit/score/cpu/m68k/qsm.h b/cpukit/score/cpu/m68k/qsm.h
new file mode 100644
index 0000000000..5cbd1375eb
--- /dev/null
+++ b/cpukit/score/cpu/m68k/qsm.h
@@ -0,0 +1,206 @@
+/*
+ *-------------------------------------------------------------------
+ *
+ * QSM -- Queued Serial Module
+ *
+ * The QSM contains two serial interfaces: (a) the queued serial
+ * peripheral interface (QSPI) and the serial communication interface
+ * (SCI). The QSPI provides peripheral expansion and/or interprocessor
+ * communication through a full-duplex, synchronous, three-wire bus. A
+ * self contained RAM queue permits serial data transfers without CPU
+ * intervention and automatic continuous sampling. The SCI provides a
+ * standard non-return to zero mark/space format with wakeup functions
+ * to allow the CPU to run uninterrupted until woken
+ *
+ * For more information, refer to Motorola's "Modular Microcontroller
+ * Family Queued Serial Module Reference Manual" (Motorola document
+ * QSMRM/AD).
+ *
+ * This file has been created by John S. Gwynne for support of
+ * Motorola's 68332 MCU in the efi332 project.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the following conditions are met:
+ * 1. Redistribution of source code and documentation must retain
+ * the above authorship, this list of conditions and the
+ * following disclaimer.
+ * 2. The name of the author may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * This software is provided "AS IS" without warranty of any kind,
+ * either expressed or implied, including, but not limited to, the
+ * implied warranties of merchantability, title and fitness for a
+ * particular purpose.
+ *
+ *------------------------------------------------------------------
+ */
+#ifndef _QSM_H_
+#define _QSM_H_
+
+
+#include <efi332.h>
+
+
+/* SAM-- shift and mask */
+#undef SAM
+#define SAM(a,b,c) ((a << b) & c)
+
+
+/* QSM_CRB (QSM Control Register Block) base address of the QSM
+ control registers */
+#if SIM_MM == 0
+#define QSM_CRB 0x7ffc00
+#else
+#undef SIM_MM
+#define SIM_MM 1
+#define QSM_CRB 0xfffc00
+#endif
+
+
+#define QSMCR (volatile unsigned short int * const)(0x00 + QSM_CRB)
+ /* QSM Configuration Register */
+#define STOP 0x8000 /* Stop Enable */
+#define FRZ 0x6000 /* Freeze Control */
+#define SUPV 0x0080 /* Supervisor/Unrestricted */
+#define IARB 0x000f /* Inerrupt Arbitration */
+
+
+#define QTEST (volatile unsigned short int * const)(0x02 + QSM_CRB)
+ /* QSM Test Register */
+/* Used only for factor testing */
+
+
+#define QILR (volatile unsigned char * const)(0x04 + QSM_CRB)
+ /* QSM Interrupt Level Register */
+#define ILQSPI 0x38 /* Interrupt Level for QSPI */
+#define ILSCI 0x07 /* Interrupt Level for SCI */
+
+
+#define QIVR (volatile unsigned char * const)(0x05 + QSM_CRB)
+ /* QSM Interrupt Vector Register */
+#define INTV 0xff /* Interrupt Vector Number */
+
+
+#define SCCR0 (volatile unsigned short int * const)(0x08 + QSM_CRB)
+ /* SCI Control Register 0 */
+#define SCBR 0x1fff /* SCI Baud Rate */
+
+
+#define SCCR1 (volatile unsigned short int * const)(0x0a + QSM_CRB)
+ /* SCI Control Register 1 */
+#define LOOPS 0x4000 /* Loop Mode */
+#define WOMS 0x2000 /* Wired-OR Mode for SCI Pins */
+#define ILT 0x1000 /* Idle-Line Detect Type */
+#define PT 0x0800 /* Parity Type */
+#define PE 0x0400 /* Parity Enable */
+#define M 0x0200 /* Mode Select */
+#define WAKE 0x0100 /* Wakeup by Address Mark */
+#define TIE 0x0080 /* Transmit Complete Interrupt Enable */
+#define TCIE 0x0040 /* Transmit Complete Interrupt Enable */
+#define RIE 0x0020 /* Receiver Interrupt Enable */
+#define ILIE 0x0010 /* Idle-Line Interrupt Enable */
+#define TE 0x0008 /* Transmitter Enable */
+#define RE 0x0004 /* Receiver Enable */
+#define RWU 0x0002 /* Receiver Wakeup */
+#define SBK 0x0001 /* Send Break */
+
+
+#define SCSR (volatile unsigned short int * const)(0x0c + QSM_CRB)
+ /* SCI Status Register */
+#define TDRE 0x0100 /* Transmit Data Register Empty */
+#define TC 0x0080 /* Transmit Complete */
+#define RDRF 0x0040 /* Receive Data Register Full */
+#define RAF 0x0020 /* Receiver Active */
+#define IDLE 0x0010 /* Idle-Line Detected */
+#define OR 0x0008 /* Overrun Error */
+#define NF 0x0004 /* Noise Error Flag */
+#define FE 0x0002 /* Framing Error */
+#define PF 0x0001 /* Parity Error */
+
+
+#define SCDR (volatile unsigned short int * const)(0x0e + QSM_CRB)
+ /* SCI Data Register */
+
+
+#define PORTQS (volatile unsigned char * const)(0x15 + QSM_CRB)
+ /* Port QS Data Register */
+
+#define PQSPAR (volatile unsigned char * const)(0x16 + QSM_CRB)
+ /* PORT QS Pin Assignment Rgister */
+/* Any bit cleared (zero) defines the corresponding pin to be an I/O
+ pin. Any bit set defines the corresponding pin to be a QSPI
+ signal. */
+/* note: PQS2 is a digital I/O pin unless the SPI is enabled in which
+ case it becomes the SPI serial clock SCK. */
+/* note: PQS7 is a digital I/O pin unless the SCI transmitter is
+ enabled in which case it becomes the SCI serial output TxD. */
+#define QSMFun 0x0
+#define QSMDis 0x1
+/*
+ * PQSPAR Field | QSM Function | Discrete I/O pin
+ *------------------+--------------+------------------ */
+#define PQSPA0 0 /* MISO | PQS0 */
+#define PQSPA1 1 /* MOSI | PQS1 */
+#define PQSPA2 2 /* SCK | PQS2 (see note)*/
+#define PQSPA3 3 /* PCSO/!SS | PQS3 */
+#define PQSPA4 4 /* PCS1 | PQS4 */
+#define PQSPA5 5 /* PCS2 | PQS5 */
+#define PQSPA6 6 /* PCS3 | PQS6 */
+#define PQSPA7 7 /* TxD | PQS7 (see note)*/
+
+
+#define DDRQS (volatile unsigned char * const)(0x17 + QSM_CRB)
+ /* PORT QS Data Direction Register */
+/* Clearing a bit makes the corresponding pin an input; setting a bit
+ makes the pin an output. */
+
+
+#define SPCR0 (volatile unsigned short int * const)(0x18 + QSM_CRB)
+ /* QSPI Control Register 0 */
+#define MSTR 0x8000 /* Master/Slave Mode Select */
+#define WOMQ 0x4000 /* Wired-OR Mode for QSPI Pins */
+#define BITS 0x3c00 /* Bits Per Transfer */
+#define CPOL 0x0200 /* Clock Polarity */
+#define CPHA 0x0100 /* Clock Phase */
+#define SPBR 0x00ff /* Serial Clock Baud Rate */
+
+
+#define SPCR1 (volatile unsigned short int * const)(0x1a + QSM_CRB)
+ /* QSPI Control Register 1 */
+#define SPE 0x8000 /* QSPI Enable */
+#define DSCKL 0x7f00 /* Delay before SCK */
+#define DTL 0x00ff /* Length of Delay after Transfer */
+
+
+#define SPCR2 (volatile unsigned short int * const)(0x1c + QSM_CRB)
+ /* QSPI Control Register 2 */
+#define SPIFIE 0x8000 /* SPI Finished Interrupt Enable */
+#define WREN 0x4000 /* Wrap Enable */
+#define WRTO 0x2000 /* Wrap To */
+#define ENDQP 0x0f00 /* Ending Queue Pointer */
+#define NEWQP 0x000f /* New Queue Pointer Value */
+
+
+#define SPCR3 (volatile unsigned char * const)(0x1e + QSM_CRB)
+ /* QSPI Control Register 3 */
+#define LOOPQ 0x0400 /* QSPI Loop Mode */
+#define HMIE 0x0200 /* HALTA and MODF Interrupt Enable */
+#define HALT 0x0100 /* Halt */
+
+
+#define SPSR (volatile unsigned char * const)(0x1f + QSM_CRB)
+ /* QSPI Status Register */
+#define SPIF 0x0080 /* QSPI Finished Flag */
+#define MODF 0x0040 /* Mode Fault Flag */
+#define HALTA 0x0020 /* Halt Acknowlwdge Flag */
+#define CPTQP x0000f /* Completed Queue Pointer */
+
+#define QSPIRR (volatile unsigned char * const)(0x100 + QSM_CRB)
+ /* QSPI Receive Data RAM */
+#define QSPITR (volatile unsigned char * const)(0x120 + QSM_CRB)
+ /* QSPI Transmit Data RAM */
+#define QSPIcR (volatile unsigned char * const)(0x140 + QSM_CRB)
+ /* QSPI Command RAM */
+
+#endif /* _QSM_H_ */
diff --git a/cpukit/score/cpu/m68k/rtems/m68k/qsm.h b/cpukit/score/cpu/m68k/rtems/m68k/qsm.h
new file mode 100644
index 0000000000..5cbd1375eb
--- /dev/null
+++ b/cpukit/score/cpu/m68k/rtems/m68k/qsm.h
@@ -0,0 +1,206 @@
+/*
+ *-------------------------------------------------------------------
+ *
+ * QSM -- Queued Serial Module
+ *
+ * The QSM contains two serial interfaces: (a) the queued serial
+ * peripheral interface (QSPI) and the serial communication interface
+ * (SCI). The QSPI provides peripheral expansion and/or interprocessor
+ * communication through a full-duplex, synchronous, three-wire bus. A
+ * self contained RAM queue permits serial data transfers without CPU
+ * intervention and automatic continuous sampling. The SCI provides a
+ * standard non-return to zero mark/space format with wakeup functions
+ * to allow the CPU to run uninterrupted until woken
+ *
+ * For more information, refer to Motorola's "Modular Microcontroller
+ * Family Queued Serial Module Reference Manual" (Motorola document
+ * QSMRM/AD).
+ *
+ * This file has been created by John S. Gwynne for support of
+ * Motorola's 68332 MCU in the efi332 project.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the following conditions are met:
+ * 1. Redistribution of source code and documentation must retain
+ * the above authorship, this list of conditions and the
+ * following disclaimer.
+ * 2. The name of the author may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * This software is provided "AS IS" without warranty of any kind,
+ * either expressed or implied, including, but not limited to, the
+ * implied warranties of merchantability, title and fitness for a
+ * particular purpose.
+ *
+ *------------------------------------------------------------------
+ */
+#ifndef _QSM_H_
+#define _QSM_H_
+
+
+#include <efi332.h>
+
+
+/* SAM-- shift and mask */
+#undef SAM
+#define SAM(a,b,c) ((a << b) & c)
+
+
+/* QSM_CRB (QSM Control Register Block) base address of the QSM
+ control registers */
+#if SIM_MM == 0
+#define QSM_CRB 0x7ffc00
+#else
+#undef SIM_MM
+#define SIM_MM 1
+#define QSM_CRB 0xfffc00
+#endif
+
+
+#define QSMCR (volatile unsigned short int * const)(0x00 + QSM_CRB)
+ /* QSM Configuration Register */
+#define STOP 0x8000 /* Stop Enable */
+#define FRZ 0x6000 /* Freeze Control */
+#define SUPV 0x0080 /* Supervisor/Unrestricted */
+#define IARB 0x000f /* Inerrupt Arbitration */
+
+
+#define QTEST (volatile unsigned short int * const)(0x02 + QSM_CRB)
+ /* QSM Test Register */
+/* Used only for factor testing */
+
+
+#define QILR (volatile unsigned char * const)(0x04 + QSM_CRB)
+ /* QSM Interrupt Level Register */
+#define ILQSPI 0x38 /* Interrupt Level for QSPI */
+#define ILSCI 0x07 /* Interrupt Level for SCI */
+
+
+#define QIVR (volatile unsigned char * const)(0x05 + QSM_CRB)
+ /* QSM Interrupt Vector Register */
+#define INTV 0xff /* Interrupt Vector Number */
+
+
+#define SCCR0 (volatile unsigned short int * const)(0x08 + QSM_CRB)
+ /* SCI Control Register 0 */
+#define SCBR 0x1fff /* SCI Baud Rate */
+
+
+#define SCCR1 (volatile unsigned short int * const)(0x0a + QSM_CRB)
+ /* SCI Control Register 1 */
+#define LOOPS 0x4000 /* Loop Mode */
+#define WOMS 0x2000 /* Wired-OR Mode for SCI Pins */
+#define ILT 0x1000 /* Idle-Line Detect Type */
+#define PT 0x0800 /* Parity Type */
+#define PE 0x0400 /* Parity Enable */
+#define M 0x0200 /* Mode Select */
+#define WAKE 0x0100 /* Wakeup by Address Mark */
+#define TIE 0x0080 /* Transmit Complete Interrupt Enable */
+#define TCIE 0x0040 /* Transmit Complete Interrupt Enable */
+#define RIE 0x0020 /* Receiver Interrupt Enable */
+#define ILIE 0x0010 /* Idle-Line Interrupt Enable */
+#define TE 0x0008 /* Transmitter Enable */
+#define RE 0x0004 /* Receiver Enable */
+#define RWU 0x0002 /* Receiver Wakeup */
+#define SBK 0x0001 /* Send Break */
+
+
+#define SCSR (volatile unsigned short int * const)(0x0c + QSM_CRB)
+ /* SCI Status Register */
+#define TDRE 0x0100 /* Transmit Data Register Empty */
+#define TC 0x0080 /* Transmit Complete */
+#define RDRF 0x0040 /* Receive Data Register Full */
+#define RAF 0x0020 /* Receiver Active */
+#define IDLE 0x0010 /* Idle-Line Detected */
+#define OR 0x0008 /* Overrun Error */
+#define NF 0x0004 /* Noise Error Flag */
+#define FE 0x0002 /* Framing Error */
+#define PF 0x0001 /* Parity Error */
+
+
+#define SCDR (volatile unsigned short int * const)(0x0e + QSM_CRB)
+ /* SCI Data Register */
+
+
+#define PORTQS (volatile unsigned char * const)(0x15 + QSM_CRB)
+ /* Port QS Data Register */
+
+#define PQSPAR (volatile unsigned char * const)(0x16 + QSM_CRB)
+ /* PORT QS Pin Assignment Rgister */
+/* Any bit cleared (zero) defines the corresponding pin to be an I/O
+ pin. Any bit set defines the corresponding pin to be a QSPI
+ signal. */
+/* note: PQS2 is a digital I/O pin unless the SPI is enabled in which
+ case it becomes the SPI serial clock SCK. */
+/* note: PQS7 is a digital I/O pin unless the SCI transmitter is
+ enabled in which case it becomes the SCI serial output TxD. */
+#define QSMFun 0x0
+#define QSMDis 0x1
+/*
+ * PQSPAR Field | QSM Function | Discrete I/O pin
+ *------------------+--------------+------------------ */
+#define PQSPA0 0 /* MISO | PQS0 */
+#define PQSPA1 1 /* MOSI | PQS1 */
+#define PQSPA2 2 /* SCK | PQS2 (see note)*/
+#define PQSPA3 3 /* PCSO/!SS | PQS3 */
+#define PQSPA4 4 /* PCS1 | PQS4 */
+#define PQSPA5 5 /* PCS2 | PQS5 */
+#define PQSPA6 6 /* PCS3 | PQS6 */
+#define PQSPA7 7 /* TxD | PQS7 (see note)*/
+
+
+#define DDRQS (volatile unsigned char * const)(0x17 + QSM_CRB)
+ /* PORT QS Data Direction Register */
+/* Clearing a bit makes the corresponding pin an input; setting a bit
+ makes the pin an output. */
+
+
+#define SPCR0 (volatile unsigned short int * const)(0x18 + QSM_CRB)
+ /* QSPI Control Register 0 */
+#define MSTR 0x8000 /* Master/Slave Mode Select */
+#define WOMQ 0x4000 /* Wired-OR Mode for QSPI Pins */
+#define BITS 0x3c00 /* Bits Per Transfer */
+#define CPOL 0x0200 /* Clock Polarity */
+#define CPHA 0x0100 /* Clock Phase */
+#define SPBR 0x00ff /* Serial Clock Baud Rate */
+
+
+#define SPCR1 (volatile unsigned short int * const)(0x1a + QSM_CRB)
+ /* QSPI Control Register 1 */
+#define SPE 0x8000 /* QSPI Enable */
+#define DSCKL 0x7f00 /* Delay before SCK */
+#define DTL 0x00ff /* Length of Delay after Transfer */
+
+
+#define SPCR2 (volatile unsigned short int * const)(0x1c + QSM_CRB)
+ /* QSPI Control Register 2 */
+#define SPIFIE 0x8000 /* SPI Finished Interrupt Enable */
+#define WREN 0x4000 /* Wrap Enable */
+#define WRTO 0x2000 /* Wrap To */
+#define ENDQP 0x0f00 /* Ending Queue Pointer */
+#define NEWQP 0x000f /* New Queue Pointer Value */
+
+
+#define SPCR3 (volatile unsigned char * const)(0x1e + QSM_CRB)
+ /* QSPI Control Register 3 */
+#define LOOPQ 0x0400 /* QSPI Loop Mode */
+#define HMIE 0x0200 /* HALTA and MODF Interrupt Enable */
+#define HALT 0x0100 /* Halt */
+
+
+#define SPSR (volatile unsigned char * const)(0x1f + QSM_CRB)
+ /* QSPI Status Register */
+#define SPIF 0x0080 /* QSPI Finished Flag */
+#define MODF 0x0040 /* Mode Fault Flag */
+#define HALTA 0x0020 /* Halt Acknowlwdge Flag */
+#define CPTQP x0000f /* Completed Queue Pointer */
+
+#define QSPIRR (volatile unsigned char * const)(0x100 + QSM_CRB)
+ /* QSPI Receive Data RAM */
+#define QSPITR (volatile unsigned char * const)(0x120 + QSM_CRB)
+ /* QSPI Transmit Data RAM */
+#define QSPIcR (volatile unsigned char * const)(0x140 + QSM_CRB)
+ /* QSPI Command RAM */
+
+#endif /* _QSM_H_ */
diff --git a/cpukit/score/cpu/m68k/rtems/m68k/sim.h b/cpukit/score/cpu/m68k/rtems/m68k/sim.h
new file mode 100644
index 0000000000..a4614e5574
--- /dev/null
+++ b/cpukit/score/cpu/m68k/rtems/m68k/sim.h
@@ -0,0 +1,325 @@
+/*
+ *-------------------------------------------------------------------
+ *
+ * SIM -- System Integration Module
+ *
+ * The system integration module (SIM) is used on many Motorola 16-
+ * and 32-bit MCUs for the following functions:
+ *
+ * () System configuration and protection. Bus and software watchdog
+ * monitors are provided in addition to periodic interrupt generators.
+ *
+ * () Clock signal generation for other intermodule bus (IMB) members
+ * and external devices.
+ *
+ * () The generation of chip-select signals that simplify external
+ * circuitry interface.
+ *
+ * () Data ports that are available for general purpose input and
+ * output.
+ *
+ * () A system test block that is intended only for factory tests.
+ *
+ * For more information, refer to Motorola's "Modular Microcontroller
+ * Family System Integration Module Reference Manual" (Motorola document
+ * SIMRM/AD).
+ *
+ * This file has been created by John S. Gwynne for support of
+ * Motorola's 68332 MCU in the efi332 project.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the following conditions are met:
+ * 1. Redistribution of source code and documentation must retain
+ * the above authorship, this list of conditions and the
+ * following disclaimer.
+ * 2. The name of the author may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * This software is provided "AS IS" without warranty of any kind,
+ * either expressed or implied, including, but not limited to, the
+ * implied warranties of merchantability, title and fitness for a
+ * particular purpose.
+ *
+ *------------------------------------------------------------------
+ */
+#ifndef _SIM_H_
+#define _SIM_H_
+
+
+#include <efi332.h>
+
+
+/* SAM-- shift and mask */
+#undef SAM
+#define SAM(a,b,c) ((a << b) & c)
+
+
+
+/* SIM_CRB (SIM Control Register Block) base address of the SIM
+ control registers */
+/* not included in ram_init.h */
+#if SIM_MM == 0
+#define SIM_CRB 0x7ffa00
+#else
+#undef SIM_MM
+#define SIM_MM 1
+#define SIM_CRB 0xfffa00
+#endif
+/* end not included in ram_init.h */
+
+
+
+#define SIMCR (volatile unsigned short int * const)(0x00 + SIM_CRB)
+ /* Module Configuration Register */
+#define EXOFF 0x8000 /* External Clock Off */
+#define FRZSW 0x4000 /* Freeze Software Enable */
+#define FRZBM 0x2000 /* Freeze Bus Monitor Enable */
+#define SLVEN 0x0800 /* Factory Test Model Enabled (ro)*/
+#define SHEN 0x0300 /* Show Cycle Enable */
+#define SUPV 0x0080 /* Supervisor/Unrestricted Data Space */
+#define MM 0x0040 /* Module Mapping */
+#define IARB 0x000f /* Interrupt Arbitration Field */
+
+
+
+#define SIMTR (volatile unsigned short int * const)(0x02 + SIM_CRB)
+ /* SIM Test Register */
+/* Used only for factor testing */
+
+
+
+#define SYNCR (volatile unsigned short int * const)(0x04 + SIM_CRB)
+ /* Clock Synthesizer Control Register */
+#define W 0x8000 /* Frequency Control (VCO) */
+#define X 0x4000 /* Frequency Control Bit (Prescale) */
+#define Y 0x3f00 /* Frequency Control Counter */
+#define EDIV 0x0080 /* ECLK Divide Rate */
+#define SLIMP 0x0010 /* Limp Mode Status */
+#define SLOCK 0x0008 /* Synthesizer Lock */
+#define RSTEN 0x0004 /* Reset Enable */
+#define STSIM 0x0002 /* Stop Mode SIM Clock */
+#define STEXT 0x0001 /* Stop Mode External Clock */
+
+
+
+#define RSR (volatile unsigned char * const)(0x07 + SIM_CRB)
+ /* Reset Status Register */
+#define EXT 0x0080 /* External Reset */
+#define POW 0x0040 /* Power-On Reset */
+#define SW 0x0020 /* Software Watchdog Reset */
+#define DBF 0x0010 /* Double Bus Fault Reset */
+#define LOC 0x0004 /* Loss of Clock Reset */
+#define SYS 0x0002 /* System Reset */
+#define TST 0x0001 /* Test Submodule Reset */
+
+
+
+#define SIMTRE (volatile unsigned short int * const)(0x08 + SIM_CRB)
+ /* System Integration Test Register */
+/* Used only for factor testing */
+
+
+
+#define PORTE0 (volatile unsigned char * const)(0x11 + SIM_CRB)
+#define PORTE1 (volatile unsigned char * const)(0x13 + SIM_CRB)
+ /* Port E Data Register */
+#define DDRE (volatile unsigned char * const)(0x15 + SIM_CRB)
+ /* Port E Data Direction Register */
+#define PEPAR (volatile unsigned char * const)(0x17 + SIM_CRB)
+ /* Port E Pin Assignment Register */
+/* Any bit cleared (zero) defines the corresponding pin to be an I/O
+ pin. Any bit set defines the corresponding pin to be a bus control
+ signal. */
+
+
+
+#define PORTF0 (volatile unsigned char * const)(0x19 + SIM_CRB)
+#define PORTF1 (volatile unsigned char * const)(0x1b + SIM_CRB)
+ /* Port F Data Register */
+#define DDRF (volatile unsigned char * const)(0x1d + SIM_CRB)
+ /* Port E Data Direction Register */
+#define PFPAR (volatile unsigned char * const)(0x1f + SIM_CRB)
+/* Any bit cleared (zero) defines the corresponding pin to be an I/O
+ pin. Any bit set defines the corresponding pin to be a bus control
+ signal. */
+
+
+
+#define SYPCR (volatile unsigned char * const)(0x21 + SIM_CRB)
+/* !!! can write to only once after reset !!! */
+ /* System Protection Control Register */
+#define SWE 0x80 /* Software Watch Enable */
+#define SWP 0x40 /* Software Watchdog Prescale */
+#define SWT 0x30 /* Software Watchdog Timing */
+#define HME 0x08 /* Halt Monitor Enable */
+#define BME 0x04 /* Bus Monitor External Enable */
+#define BMT 0x03 /* Bus Monitor Timing */
+
+
+
+#define PICR (volatile unsigned short int * const)(0x22 + SIM_CRB)
+ /* Periodic Interrupt Control Reg. */
+#define PIRQL 0x0700 /* Periodic Interrupt Request Level */
+#define PIV 0x00ff /* Periodic Interrupt Level */
+
+
+
+#define PITR (volatile unsigned short int * const)(0x24 + SIM_CRB)
+ /* Periodic Interrupt Timer Register */
+#define PTP 0x0100 /* Periodic Timer Prescaler Control */
+#define PITM 0x00ff /* Periodic Interrupt Timing Modulus */
+
+
+
+#define SWSR (volatile unsigned char * const)(0x27 + SIM_CRB)
+ /* Software Service Register */
+/* write 0x55 then 0xaa to service the software watchdog */
+
+
+
+#define TSTMSRA (volatile unsigned short int * const)(0x30 + SIM_CRB)
+ /* Test Module Master Shift A */
+#define TSTMSRB (volatile unsigned short int * const)(0x32 + SIM_CRB)
+ /* Test Module Master Shift A */
+#define TSTSC (volatile unsigned short int * const)(0x34 + SIM_CRB)
+ /* Test Module Shift Count */
+#define TSTRC (volatile unsigned short int * const)(0x36 + SIM_CRB)
+ /* Test Module Repetition Counter */
+#define CREG (volatile unsigned short int * const)(0x38 + SIM_CRB)
+ /* Test Module Control */
+#define DREG (volatile unsigned short int * const)(0x3a + SIM_CRB)
+ /* Test Module Distributed */
+/* Used only for factor testing */
+
+
+
+#define PORTC (volatile unsigned char * const)(0x41 + SIM_CRB)
+ /* Port C Data */
+
+
+
+#define CSPAR0 (volatile unsigned short int * const)(0x44 + SIM_CRB)
+ /* Chip Select Pin Assignment
+ Resgister 0 */
+/* CSPAR0 contains seven two-bit fields that determine the functions
+ of corresponding chip-select pins. CSPAR0[15:14] are not
+ used. These bits always read zero; write have no effect. CSPAR0 bit
+ 1 always reads one; writes to CSPAR0 bit 1 have no effect. */
+#define CSPAR1 (volatile unsigned short int * const)(0x46 + SIM_CRB)
+ /* Chip Select Pin Assignment
+ Register 1 */
+/* CSPAR1 contains five two-bit fields that determine the finctions of
+ corresponding chip-select pins. CSPAR1[15:10] are not used. These
+ bits always read zero; writes have no effect. */
+/*
+ *
+ * Bit Field | Description
+ * ------------+---------------
+ * 00 | Discrete Output
+ * 01 | Alternate Function
+ * 10 | Chip Select (8-bit port)
+ * 11 | Chip Select (16-bit port)
+ */
+#define DisOut 0x0
+#define AltFun 0x1
+#define CS8bit 0x2
+#define CS16bit 0x3
+/*
+ *
+ * CSPARx Field |Chip Select Signal | Alternate Signal | Discrete Output
+ *-----------------+--------------------+--------------------+---------------*/
+#define CS_5 12 /* !CS5 | FC2 | PC2 */
+#define CS_4 10 /* !CS4 | FC1 | PC1 */
+#define CS_3 8 /* !CS3 | FC0 | PC0 */
+#define CS_2 6 /* !CS2 | !BGACK | */
+#define CS_1 4 /* !CS1 | !BG | */
+#define CS_0 2 /* !CS0 | !BR | */
+#define CSBOOT 0 /* !CSBOOT | | */
+/* | | | */
+#define CS_10 8 /* !CS10 | ADDR23 | ECLK */
+#define CS_9 6 /* !CS9 | ADDR22 | PC6 */
+#define CS_8 4 /* !CS8 | ADDR21 | PC5 */
+#define CS_7 2 /* !CS7 | ADDR20 | PC4 */
+#define CS_6 0 /* !CS6 | ADDR19 | PC3 */
+
+#define BS_2K 0x0
+#define BS_8K 0x1
+#define BS_16K 0x2
+#define BS_64K 0x3
+#define BS_128K 0x4
+#define BS_256K 0x5
+#define BS_512K 0x6
+#define BS_1M 0x7
+
+#define CSBARBT (volatile unsigned short int * const)(0x48 + SIM_CRB)
+#define CSBAR0 (volatile unsigned short int * const)(0x4c + SIM_CRB)
+#define CSBAR1 (volatile unsigned short int * const)(0x50 + SIM_CRB)
+#define CSBAR2 (volatile unsigned short int * const)(0x54 + SIM_CRB)
+#define CSBAR3 (volatile unsigned short int * const)(0x58 + SIM_CRB)
+#define CSBAR4 (volatile unsigned short int * const)(0x5c + SIM_CRB)
+#define CSBAR5 (volatile unsigned short int * const)(0x60 + SIM_CRB)
+#define CSBAR6 (volatile unsigned short int * const)(0x64 + SIM_CRB)
+#define CSBAR7 (volatile unsigned short int * const)(0x68 + SIM_CRB)
+#define CSBAR8 (volatile unsigned short int * const)(0x6c + SIM_CRB)
+#define CSBAR9 (volatile unsigned short int * const)(0x70 + SIM_CRB)
+#define CSBAR10 (volatile unsigned short int * const)(0x74 + SIM_CRB)
+
+#define MODE 0x8000
+#define Disable 0
+#define LowerByte 0x2000
+#define UpperByte 0x4000
+#define BothBytes 0x6000
+#define ReadOnly 0x0800
+#define WriteOnly 0x1000
+#define ReadWrite 0x1800
+#define SyncAS 0x0
+#define SyncDS 0x0400
+
+#define WaitStates_0 (0x0 << 6)
+#define WaitStates_1 (0x1 << 6)
+#define WaitStates_2 (0x2 << 6)
+#define WaitStates_3 (0x3 << 6)
+#define WaitStates_4 (0x4 << 6)
+#define WaitStates_5 (0x5 << 6)
+#define WaitStates_6 (0x6 << 6)
+#define WaitStates_7 (0x7 << 6)
+#define WaitStates_8 (0x8 << 6)
+#define WaitStates_9 (0x9 << 6)
+#define WaitStates_10 (0xa << 6)
+#define WaitStates_11 (0xb << 6)
+#define WaitStates_12 (0xc << 6)
+#define WaitStates_13 (0xd << 6)
+#define FastTerm (0xe << 6)
+#define External (0xf << 6)
+
+#define CPUSpace (0x0 << 4)
+#define UserSpace (0x1 << 4)
+#define SupSpace (0x2 << 4)
+#define UserSupSpace (0x3 << 4)
+
+#define IPLevel_any 0x0
+#define IPLevel_1 0x2
+#define IPLevel_2 0x4
+#define IPLevel_3 0x6
+#define IPLevel_4 0x8
+#define IPLevel_5 0xa
+#define IPLevel_6 0xc
+#define IPLevel_7 0xe
+
+#define AVEC 1
+
+#define CSORBT (volatile unsigned short int * const)(0x4a + SIM_CRB)
+#define CSOR0 (volatile unsigned short int * const)(0x4e + SIM_CRB)
+#define CSOR1 (volatile unsigned short int * const)(0x52 + SIM_CRB)
+#define CSOR2 (volatile unsigned short int * const)(0x56 + SIM_CRB)
+#define CSOR3 (volatile unsigned short int * const)(0x5a + SIM_CRB)
+#define CSOR4 (volatile unsigned short int * const)(0x5e + SIM_CRB)
+#define CSOR5 (volatile unsigned short int * const)(0x62 + SIM_CRB)
+#define CSOR6 (volatile unsigned short int * const)(0x66 + SIM_CRB)
+#define CSOR7 (volatile unsigned short int * const)(0x6a + SIM_CRB)
+#define CSOR8 (volatile unsigned short int * const)(0x6e + SIM_CRB)
+#define CSOR9 (volatile unsigned short int * const)(0x72 + SIM_CRB)
+#define CSOR10 (volatile unsigned short int * const)(0x76 + SIM_CRB)
+
+#endif /* _SIM_h_ */
diff --git a/cpukit/score/cpu/m68k/sim.h b/cpukit/score/cpu/m68k/sim.h
new file mode 100644
index 0000000000..a4614e5574
--- /dev/null
+++ b/cpukit/score/cpu/m68k/sim.h
@@ -0,0 +1,325 @@
+/*
+ *-------------------------------------------------------------------
+ *
+ * SIM -- System Integration Module
+ *
+ * The system integration module (SIM) is used on many Motorola 16-
+ * and 32-bit MCUs for the following functions:
+ *
+ * () System configuration and protection. Bus and software watchdog
+ * monitors are provided in addition to periodic interrupt generators.
+ *
+ * () Clock signal generation for other intermodule bus (IMB) members
+ * and external devices.
+ *
+ * () The generation of chip-select signals that simplify external
+ * circuitry interface.
+ *
+ * () Data ports that are available for general purpose input and
+ * output.
+ *
+ * () A system test block that is intended only for factory tests.
+ *
+ * For more information, refer to Motorola's "Modular Microcontroller
+ * Family System Integration Module Reference Manual" (Motorola document
+ * SIMRM/AD).
+ *
+ * This file has been created by John S. Gwynne for support of
+ * Motorola's 68332 MCU in the efi332 project.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the following conditions are met:
+ * 1. Redistribution of source code and documentation must retain
+ * the above authorship, this list of conditions and the
+ * following disclaimer.
+ * 2. The name of the author may not be used to endorse or promote
+ * products derived from this software without specific prior
+ * written permission.
+ *
+ * This software is provided "AS IS" without warranty of any kind,
+ * either expressed or implied, including, but not limited to, the
+ * implied warranties of merchantability, title and fitness for a
+ * particular purpose.
+ *
+ *------------------------------------------------------------------
+ */
+#ifndef _SIM_H_
+#define _SIM_H_
+
+
+#include <efi332.h>
+
+
+/* SAM-- shift and mask */
+#undef SAM
+#define SAM(a,b,c) ((a << b) & c)
+
+
+
+/* SIM_CRB (SIM Control Register Block) base address of the SIM
+ control registers */
+/* not included in ram_init.h */
+#if SIM_MM == 0
+#define SIM_CRB 0x7ffa00
+#else
+#undef SIM_MM
+#define SIM_MM 1
+#define SIM_CRB 0xfffa00
+#endif
+/* end not included in ram_init.h */
+
+
+
+#define SIMCR (volatile unsigned short int * const)(0x00 + SIM_CRB)
+ /* Module Configuration Register */
+#define EXOFF 0x8000 /* External Clock Off */
+#define FRZSW 0x4000 /* Freeze Software Enable */
+#define FRZBM 0x2000 /* Freeze Bus Monitor Enable */
+#define SLVEN 0x0800 /* Factory Test Model Enabled (ro)*/
+#define SHEN 0x0300 /* Show Cycle Enable */
+#define SUPV 0x0080 /* Supervisor/Unrestricted Data Space */
+#define MM 0x0040 /* Module Mapping */
+#define IARB 0x000f /* Interrupt Arbitration Field */
+
+
+
+#define SIMTR (volatile unsigned short int * const)(0x02 + SIM_CRB)
+ /* SIM Test Register */
+/* Used only for factor testing */
+
+
+
+#define SYNCR (volatile unsigned short int * const)(0x04 + SIM_CRB)
+ /* Clock Synthesizer Control Register */
+#define W 0x8000 /* Frequency Control (VCO) */
+#define X 0x4000 /* Frequency Control Bit (Prescale) */
+#define Y 0x3f00 /* Frequency Control Counter */
+#define EDIV 0x0080 /* ECLK Divide Rate */
+#define SLIMP 0x0010 /* Limp Mode Status */
+#define SLOCK 0x0008 /* Synthesizer Lock */
+#define RSTEN 0x0004 /* Reset Enable */
+#define STSIM 0x0002 /* Stop Mode SIM Clock */
+#define STEXT 0x0001 /* Stop Mode External Clock */
+
+
+
+#define RSR (volatile unsigned char * const)(0x07 + SIM_CRB)
+ /* Reset Status Register */
+#define EXT 0x0080 /* External Reset */
+#define POW 0x0040 /* Power-On Reset */
+#define SW 0x0020 /* Software Watchdog Reset */
+#define DBF 0x0010 /* Double Bus Fault Reset */
+#define LOC 0x0004 /* Loss of Clock Reset */
+#define SYS 0x0002 /* System Reset */
+#define TST 0x0001 /* Test Submodule Reset */
+
+
+
+#define SIMTRE (volatile unsigned short int * const)(0x08 + SIM_CRB)
+ /* System Integration Test Register */
+/* Used only for factor testing */
+
+
+
+#define PORTE0 (volatile unsigned char * const)(0x11 + SIM_CRB)
+#define PORTE1 (volatile unsigned char * const)(0x13 + SIM_CRB)
+ /* Port E Data Register */
+#define DDRE (volatile unsigned char * const)(0x15 + SIM_CRB)
+ /* Port E Data Direction Register */
+#define PEPAR (volatile unsigned char * const)(0x17 + SIM_CRB)
+ /* Port E Pin Assignment Register */
+/* Any bit cleared (zero) defines the corresponding pin to be an I/O
+ pin. Any bit set defines the corresponding pin to be a bus control
+ signal. */
+
+
+
+#define PORTF0 (volatile unsigned char * const)(0x19 + SIM_CRB)
+#define PORTF1 (volatile unsigned char * const)(0x1b + SIM_CRB)
+ /* Port F Data Register */
+#define DDRF (volatile unsigned char * const)(0x1d + SIM_CRB)
+ /* Port E Data Direction Register */
+#define PFPAR (volatile unsigned char * const)(0x1f + SIM_CRB)
+/* Any bit cleared (zero) defines the corresponding pin to be an I/O
+ pin. Any bit set defines the corresponding pin to be a bus control
+ signal. */
+
+
+
+#define SYPCR (volatile unsigned char * const)(0x21 + SIM_CRB)
+/* !!! can write to only once after reset !!! */
+ /* System Protection Control Register */
+#define SWE 0x80 /* Software Watch Enable */
+#define SWP 0x40 /* Software Watchdog Prescale */
+#define SWT 0x30 /* Software Watchdog Timing */
+#define HME 0x08 /* Halt Monitor Enable */
+#define BME 0x04 /* Bus Monitor External Enable */
+#define BMT 0x03 /* Bus Monitor Timing */
+
+
+
+#define PICR (volatile unsigned short int * const)(0x22 + SIM_CRB)
+ /* Periodic Interrupt Control Reg. */
+#define PIRQL 0x0700 /* Periodic Interrupt Request Level */
+#define PIV 0x00ff /* Periodic Interrupt Level */
+
+
+
+#define PITR (volatile unsigned short int * const)(0x24 + SIM_CRB)
+ /* Periodic Interrupt Timer Register */
+#define PTP 0x0100 /* Periodic Timer Prescaler Control */
+#define PITM 0x00ff /* Periodic Interrupt Timing Modulus */
+
+
+
+#define SWSR (volatile unsigned char * const)(0x27 + SIM_CRB)
+ /* Software Service Register */
+/* write 0x55 then 0xaa to service the software watchdog */
+
+
+
+#define TSTMSRA (volatile unsigned short int * const)(0x30 + SIM_CRB)
+ /* Test Module Master Shift A */
+#define TSTMSRB (volatile unsigned short int * const)(0x32 + SIM_CRB)
+ /* Test Module Master Shift A */
+#define TSTSC (volatile unsigned short int * const)(0x34 + SIM_CRB)
+ /* Test Module Shift Count */
+#define TSTRC (volatile unsigned short int * const)(0x36 + SIM_CRB)
+ /* Test Module Repetition Counter */
+#define CREG (volatile unsigned short int * const)(0x38 + SIM_CRB)
+ /* Test Module Control */
+#define DREG (volatile unsigned short int * const)(0x3a + SIM_CRB)
+ /* Test Module Distributed */
+/* Used only for factor testing */
+
+
+
+#define PORTC (volatile unsigned char * const)(0x41 + SIM_CRB)
+ /* Port C Data */
+
+
+
+#define CSPAR0 (volatile unsigned short int * const)(0x44 + SIM_CRB)
+ /* Chip Select Pin Assignment
+ Resgister 0 */
+/* CSPAR0 contains seven two-bit fields that determine the functions
+ of corresponding chip-select pins. CSPAR0[15:14] are not
+ used. These bits always read zero; write have no effect. CSPAR0 bit
+ 1 always reads one; writes to CSPAR0 bit 1 have no effect. */
+#define CSPAR1 (volatile unsigned short int * const)(0x46 + SIM_CRB)
+ /* Chip Select Pin Assignment
+ Register 1 */
+/* CSPAR1 contains five two-bit fields that determine the finctions of
+ corresponding chip-select pins. CSPAR1[15:10] are not used. These
+ bits always read zero; writes have no effect. */
+/*
+ *
+ * Bit Field | Description
+ * ------------+---------------
+ * 00 | Discrete Output
+ * 01 | Alternate Function
+ * 10 | Chip Select (8-bit port)
+ * 11 | Chip Select (16-bit port)
+ */
+#define DisOut 0x0
+#define AltFun 0x1
+#define CS8bit 0x2
+#define CS16bit 0x3
+/*
+ *
+ * CSPARx Field |Chip Select Signal | Alternate Signal | Discrete Output
+ *-----------------+--------------------+--------------------+---------------*/
+#define CS_5 12 /* !CS5 | FC2 | PC2 */
+#define CS_4 10 /* !CS4 | FC1 | PC1 */
+#define CS_3 8 /* !CS3 | FC0 | PC0 */
+#define CS_2 6 /* !CS2 | !BGACK | */
+#define CS_1 4 /* !CS1 | !BG | */
+#define CS_0 2 /* !CS0 | !BR | */
+#define CSBOOT 0 /* !CSBOOT | | */
+/* | | | */
+#define CS_10 8 /* !CS10 | ADDR23 | ECLK */
+#define CS_9 6 /* !CS9 | ADDR22 | PC6 */
+#define CS_8 4 /* !CS8 | ADDR21 | PC5 */
+#define CS_7 2 /* !CS7 | ADDR20 | PC4 */
+#define CS_6 0 /* !CS6 | ADDR19 | PC3 */
+
+#define BS_2K 0x0
+#define BS_8K 0x1
+#define BS_16K 0x2
+#define BS_64K 0x3
+#define BS_128K 0x4
+#define BS_256K 0x5
+#define BS_512K 0x6
+#define BS_1M 0x7
+
+#define CSBARBT (volatile unsigned short int * const)(0x48 + SIM_CRB)
+#define CSBAR0 (volatile unsigned short int * const)(0x4c + SIM_CRB)
+#define CSBAR1 (volatile unsigned short int * const)(0x50 + SIM_CRB)
+#define CSBAR2 (volatile unsigned short int * const)(0x54 + SIM_CRB)
+#define CSBAR3 (volatile unsigned short int * const)(0x58 + SIM_CRB)
+#define CSBAR4 (volatile unsigned short int * const)(0x5c + SIM_CRB)
+#define CSBAR5 (volatile unsigned short int * const)(0x60 + SIM_CRB)
+#define CSBAR6 (volatile unsigned short int * const)(0x64 + SIM_CRB)
+#define CSBAR7 (volatile unsigned short int * const)(0x68 + SIM_CRB)
+#define CSBAR8 (volatile unsigned short int * const)(0x6c + SIM_CRB)
+#define CSBAR9 (volatile unsigned short int * const)(0x70 + SIM_CRB)
+#define CSBAR10 (volatile unsigned short int * const)(0x74 + SIM_CRB)
+
+#define MODE 0x8000
+#define Disable 0
+#define LowerByte 0x2000
+#define UpperByte 0x4000
+#define BothBytes 0x6000
+#define ReadOnly 0x0800
+#define WriteOnly 0x1000
+#define ReadWrite 0x1800
+#define SyncAS 0x0
+#define SyncDS 0x0400
+
+#define WaitStates_0 (0x0 << 6)
+#define WaitStates_1 (0x1 << 6)
+#define WaitStates_2 (0x2 << 6)
+#define WaitStates_3 (0x3 << 6)
+#define WaitStates_4 (0x4 << 6)
+#define WaitStates_5 (0x5 << 6)
+#define WaitStates_6 (0x6 << 6)
+#define WaitStates_7 (0x7 << 6)
+#define WaitStates_8 (0x8 << 6)
+#define WaitStates_9 (0x9 << 6)
+#define WaitStates_10 (0xa << 6)
+#define WaitStates_11 (0xb << 6)
+#define WaitStates_12 (0xc << 6)
+#define WaitStates_13 (0xd << 6)
+#define FastTerm (0xe << 6)
+#define External (0xf << 6)
+
+#define CPUSpace (0x0 << 4)
+#define UserSpace (0x1 << 4)
+#define SupSpace (0x2 << 4)
+#define UserSupSpace (0x3 << 4)
+
+#define IPLevel_any 0x0
+#define IPLevel_1 0x2
+#define IPLevel_2 0x4
+#define IPLevel_3 0x6
+#define IPLevel_4 0x8
+#define IPLevel_5 0xa
+#define IPLevel_6 0xc
+#define IPLevel_7 0xe
+
+#define AVEC 1
+
+#define CSORBT (volatile unsigned short int * const)(0x4a + SIM_CRB)
+#define CSOR0 (volatile unsigned short int * const)(0x4e + SIM_CRB)
+#define CSOR1 (volatile unsigned short int * const)(0x52 + SIM_CRB)
+#define CSOR2 (volatile unsigned short int * const)(0x56 + SIM_CRB)
+#define CSOR3 (volatile unsigned short int * const)(0x5a + SIM_CRB)
+#define CSOR4 (volatile unsigned short int * const)(0x5e + SIM_CRB)
+#define CSOR5 (volatile unsigned short int * const)(0x62 + SIM_CRB)
+#define CSOR6 (volatile unsigned short int * const)(0x66 + SIM_CRB)
+#define CSOR7 (volatile unsigned short int * const)(0x6a + SIM_CRB)
+#define CSOR8 (volatile unsigned short int * const)(0x6e + SIM_CRB)
+#define CSOR9 (volatile unsigned short int * const)(0x72 + SIM_CRB)
+#define CSOR10 (volatile unsigned short int * const)(0x76 + SIM_CRB)
+
+#endif /* _SIM_h_ */