2008-10-28 Joel Sherrill <joel.sherrill@oarcorp.com>

	* Makefile.am, preinstall.am, rtems/score/cpu.h: Now performs context
	switches and many tests run.
	* context_init.c, context_switch.S, cpu.c, cpu_asm.c: New files.

1 files changed, 93 insertions, 0 deletions

diff --git a/cpukit/score/cpu/m32r/cpu_asm.c b/cpukit/score/cpu/m32r/cpu_asm.c
new file mode 100644
index 0000000000..11e7af58ca
--- /dev/null
+++ b/cpukit/score/cpu/m32r/cpu_asm.c
@@ -0,0 +1,93 @@
+/*  cpu_asm.c  ===> cpu_asm.S or cpu_asm.s
+ *
+ *  NOTE:  This is supposed to be a .S or .s file NOT a C file.
+ *
+ *  M32R does not yet have interrupt support.  When this functionality
+ *  is written, this file should become obsolete.
+ *
+ *  COPYRIGHT (c) 1989-2008.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/cpu.h>
+
+/*  void __ISR_Handler()
+ *
+ *  This routine provides the RTEMS interrupt management.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _ISR_Handler(void)
+{
+   /*
+    *  This discussion ignores a lot of the ugly details in a real
+    *  implementation such as saving enough registers/state to be
+    *  able to do something real.  Keep in mind that the goal is
+    *  to invoke a user's ISR handler which is written in C and
+    *  uses a certain set of registers.
+    *
+    *  Also note that the exact order is to a large extent flexible.
+    *  Hardware will dictate a sequence for a certain subset of
+    *  _ISR_Handler while requirements for setting
+    */
+
+  /*
+   *  At entry to "common" _ISR_Handler, the vector number must be
+   *  available.  On some CPUs the hardware puts either the vector
+   *  number or the offset into the vector table for this ISR in a
+   *  known place.  If the hardware does not give us this information,
+   *  then the assembly portion of RTEMS for this port will contain
+   *  a set of distinct interrupt entry points which somehow place
+   *  the vector number in a known place (which is safe if another
+   *  interrupt nests this one) and branches to _ISR_Handler.
+   *
+   *  save some or all context on stack
+   *  may need to save some special interrupt information for exit
+   *
+   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
+   *    if ( _ISR_Nest_level == 0 )
+   *      switch to software interrupt stack
+   *  #endif
+   *
+   *  _ISR_Nest_level++;
+   *
+   *  _Thread_Dispatch_disable_level++;
+   *
+   *  (*_ISR_Vector_table[ vector ])( vector );
+   *
+   *  _Thread_Dispatch_disable_level--;
+   *
+   *  --_ISR_Nest_level;
+   *
+   *  if ( _ISR_Nest_level )
+   *    goto the label "exit interrupt (simple case)"
+   *
+   *  if ( _Thread_Dispatch_disable_level )
+   *    _ISR_Signals_to_thread_executing = FALSE;
+   *    goto the label "exit interrupt (simple case)"
+   *
+   *  if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
+   *    _ISR_Signals_to_thread_executing = FALSE;
+   *    call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
+   *    prepare to get out of interrupt
+   *    return from interrupt  (maybe to _ISR_Dispatch)
+   *
+   *  LABEL "exit interrupt (simple case):
+   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
+   *    if outermost interrupt 
+   *      restore stack
+   *  #endif
+   *  prepare to get out of interrupt
+   *  return from interrupt
+   */
+}